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Patent # Description
US-1,006,1730 Routing of messages
A method to provide transfer of data without the use of a network from an application program to an embedded device. A routing service establishes a...
US-1,006,1729 Scalable multi-core system-on-chip architecture on multiple dice for high end microcontroller
A system for a multiple chip architecture that enables different system on-chip (SoC) systems with varying compatibilities to interact as one SoC via a...
US-1,006,1728 Arbitration and hazard detection for a data processing apparatus
A device for selecting requests to be serviced in a data processing apparatus has an arbitration stage for selecting an arbitrated request from a plurality of...
US-1,006,1727 Enhanced queue management
A paired queue apparatus and method comprising request and response queues wherein queue head and tail pointer update values are communicated through an...
US-1,006,1726 Precision time management (PTM) for USB retimers that accurately adjusts timestamp fields of isochronous...
A system and method of conducting precision time management in a universal serial bus system with a retimer. The method includes initiating, from the retimer, a...
US-1,006,1725 Scanning memory for de-duplication using RDMA
A method for storage includes storing multiple memory pages in a memory of a first compute node. Using a second compute node that communicates with the first...
US-1,006,1724 Latency reduction for direct memory access operations involving address translation
Latency reduction for direct memory access operations involving address translation is disclosed. Example methods disclosed herein to perform direct memory...
US-1,006,1723 Techniques for handling queued interrupts in a data processing system based on a saturation value
A technique for handling queued interrupts includes accumulating, by an interrupt routing controller (IRC), respective backlog counts for respective event...
US-1,006,1722 Method to handle concurrent fatal events in a multicore execution environment
Techniques for handling concurrent fatal events in a multicore execution environment are described. An example method for handling interrupts in a processor...
US-1,006,1721 System of data handling based on periodic interruptions to electricity supply
An approach to data handling based upon the temporal extents of the interruptions to supply of electricity to selected components is provided. At present,...
US-1,006,1720 Storage system and signal transfer method
A storage system includes a controller part, a data storage part, and a transfer path of a signal that couples these parts. A driver included in the controller...
US-1,006,1719 Packed write completions
A plurality of completed writes to memory are identified corresponding to a plurality of write requests from a host device received over a buffered memory...
US-1,006,1718 Protecting secret state from memory attacks
Described is a technology by which classes of memory attacks are prevented, including cold boot attacks, DMA attacks, and bus monitoring attacks. In general,...
US-1,006,1717 Storing multiple encryption keys to protect data at rest
Techniques of protecting data involve storing a data structure in a data storage system that associates indices with respective keys. In this data structure,...
US-1,006,1716 Storage device authentication
Systems and methods authenticate storage devices. In one implementation, a computer-implemented method is provided for authenticating a storage device....
US-1,006,1715 Structure-preserving subgraph queries
The present invention relates to solving the issues related to subgraph query services with tunable preservation of privacy of structural information. More...
US-1,006,1714 Tuple encoding aware direct memory access engine for scratchpad enabled multicore processors
Techniques are described herein for efficient movement of data from a source memory to a destination memory. In an embodiment, in response to a particular...
US-1,006,1713 Associating cache memory with a work process
Systems, methods, and software described herein provide accelerated input and output of data in a work process. In one example, a method of operating a support...
US-1,006,1712 Virtual memory page mapping overlays
In some embodiments, a memory overlay system comprises a translation lookaside buffer (TLB) that includes an entry that specifies a virtual address range that...
US-1,006,1711 File access method and apparatus, and storage system
A file access method and apparatus, and a storage system are provided. After receiving a file access request from a process, a first physical address space is...
US-1,006,1710 Storage device
The present invention provides a storage device adopting a semiconductor device as a storage media having a nonvolatile property and must be erased for writing...
US-1,006,1709 Systems and methods for accessing memory
Methods of mapping memory cells to applications, methods of accessing memory cells, systems, and memory controllers are described. In some embodiments, a memory...
US-1,006,1708 Mapped region table
Techniques and systems for first determining if a non-volatile memory configured to store physical data pages is being initialized, and a volatile memory...
US-1,006,1707 Speculative enumeration of bus-device-function address space
A first device is determined as connected to a first one of a plurality of ports of a root complex. Addresses are assigned corresponding to a first hierarchy of...
US-1,006,1706 System and method for eviction and replacement in large content-addressable flash caches
In a processing system in which at least one entity issues data read and write requests to at least one storage system that stores data as data units,...
US-1,006,1705 Identifying instructions for decode-time instruction optimization grouping in view of cache boundaries
A technique for processing instructions includes examining instructions in an instruction stream of a processor to determine properties of the instructions. The...
US-1,006,1704 Systems and methods for managing cache of a data storage device
A data storage device includes a data storage medium having a plurality of data blocks. A cache includes a plurality of cache blocks. Each cache block includes...
US-1,006,1703 Prefetch insensitive transactional memory
Prevention of a prefetch memory operation from causing a transaction to abort. A local processor receives a prefetch request from a remote processor. A...
US-1,006,1702 Predictive analytics for storage tiering and caching
Various embodiments for data management across a multiple-tiered storage organization by a processor. Data operations performed across the multiple-tiered...
US-1,006,1701 Sharing of class data among virtual machine applications running on guests in virtualized environment using...
A method, system and computer program product for sharing class data among virtual machine applications running on one or more guests in a virtualized...
US-1,006,1700 System and method for managing transactions
A method for writing data, the method may include: receiving or generating, by an interfacing module, a data unit coherent write request for performing a...
US-1,006,1699 Multiple data channel memory module architecture
According to one example of the present disclosure, a system includes a computing element configured to provide requests for memory access operations and a...
US-1,006,1698 Reducing or avoiding buffering of evicted cache data from an uncompressed cache memory in a compression memory...
Aspects disclosed involve reducing or avoiding buffering of evicted cache data from an uncompressed cache memory in a compression memory system when stalled...
US-1,006,1697 Garbage collection scope detection for distributed storage
Systems and methods for determining garbage collection (GC) scope in a distribute storage system using chunk-based storage. The systems and methods are...
US-1,006,1696 Partial garbage collection for fast error handling and optimized garbage collection for the invisible band
A method for managing garbage collection of memory locations in an DSD having a plurality of dies each having a plurality of memory blocks includes: selecting a...
US-1,006,1695 Memory system and operating method thereof
Provided herein are a memory system and an operating method thereof. A method of operating a controller for controlling a memory block including a plurality of...
US-1,006,1694 Memory system and method for controlling non-volatile memory
According to one embodiment, a memory system perform a first write operation for writing data to a non-volatile memory by a first write method for writing...
US-1,006,1693 Method of generating secondary index and apparatus for storing secondary index
A method and apparatus for generating and storing a secondary index. The method includes generating, in response to a size of an index data being greater than a...
US-1,006,1692 Method and system for automated storage provisioning
Example embodiments of the present invention include a method, a system, and a computer-program product for storage automation. The method includes receiving a...
US-1,006,1691 Write data optimization methods for non-volatile semiconductor memory devices
According to one embodiment, a controller writes first processed data acquired by a first process into a nonvolatile memory during a first period. The...
US-1,006,1690 Computing device and method for performing test of rehosting
Disclosed is a method for performing a test of rehosting performed by a computing device including one or more processors and a memory storing commands...
US-1,006,1689 Distributed software testing
Technologies are disclosed herein for distributed software testing. A software testing service is disclosed that can receive tests for software under test. The...
US-1,006,1688 Method and system to automatically enforce a hybrid branching strategy
A method and system for automatically enforcing a hybrid branching strategy include receiving a changeset designated for a branch. In response to receiving the...
US-1,006,1687 Self-learning and self-validating declarative testing
A system and method for self-learning and self-validating declarative testing are provided. In example embodiments, a user experience module identifies a...
US-1,006,1686 Method, electronic apparatus, system, and storage medium for automated testing of application user interface
The present disclosure provides a method for automated testing of an application user interface, being implemented in an electronic apparatus, including:...
US-1,006,1685 System, method, and computer program for high volume test automation (HVTA) utilizing recorded automation...
A system, method, and computer program product are provided for High Volume Test Automation (HVTA) utilizing recorded automation building blocks. In operation,...
US-1,006,1684 Enhanced service validation
Technology is disclosed herein for validating a new version of a service running in parallel with a previous version of the service. In a validation...
US-1,006,1683 Systems and methods for collecting error data to troubleshoot product errors
The disclosed computer-implemented method for collecting error data to troubleshoot product errors may include (1) monitoring Internet searches submitted by a...
US-1,006,1682 Detecting race condition vulnerabilities in computer software applications
Testing computer software applications is performed by identifying first and second executable portions of the computer software application, where the portions...
US-1,006,1681 System for discovering bugs using interval algebra query language
A system for discovering bugs comprises an input interface and a processor. The input interface is configured to receive a bug definition. The bug definition...
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