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Patent # Description
US-1,006,9011 Method for fabricating a FinFET metallization architecture using a self-aligned contact etch
A method of fabricating a FinFET device includes a self-aligned contact etch where a source/drain contact module is performed prior to a replacement metal gate...
US-1,006,9010 Semiconductor device having compressively strained channel region and method of making same
A semiconductor device and method making it utilize a three-dimensional channel region comprising a core of a first semiconductor material and an epitaxial...
US-1,006,9009 Method for forming recess within epitaxial layer
A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first recess adjacent to two sides of...
US-1,006,9008 Vertical transistor pass gate device
A semiconductor device including a fin structure present on a supporting substrate to provide a vertically orientated channel region. A first source/drain...
US-1,006,9007 Vertical FETs with high density capacitor
A technique relates to semiconductors. A bottom terminal of a transistor and bottom plate of a capacitor are positioned on the substrate. A spacer is arranged...
US-1,006,9006 Semiconductor device with vertical field floating rings and methods of fabrication thereof
A semiconductor device includes a semiconductor substrate having a first conductivity type. A gate structure is supported by a surface of the semiconductor...
US-1,006,9005 Termination design for high voltage device
The present disclosure describes a termination structure for a high voltage semiconductor transistor device. The termination structure is composed of at least...
US-1,006,9004 Semiconductor device and method of manufacturing semiconductor device
A semiconductor device of an embodiment includes a p.sup.+-type region selectively disposed in a surface of an n-type silicon carbide epitaxial layer disposed...
US-1,006,9003 MOSFET
When a channel formation region is formed of GaN in a MOSFET, there are cases where the actual threshold voltage (V.sub.th) is lower than the setting value...
US-1,006,9002 Bond-over-active circuity gallium nitride devices
Implementations of semiconductor devices may include: a first layer with a plurality of cells, each cell having a drain finger, a source finger and a gate ring;...
US-1,006,9001 Power component protected against overheating
A triac has a vertical structure formed from a silicon substrate having an upper surface side. A main metallization on the upper surface side has a first...
US-1,006,9000 Bipolar non-punch-through power semiconductor device
The invention relates to a bipolar non-punch-through power semiconductor device and a corresponding manufacturing method. The device comprises a semiconductor...
US-1,006,8999 Vertical power component
A high-voltage vertical power component including a silicon substrate of a first conductivity type, and a first semiconductor layer of the second conductivity...
US-1,006,8998 Semiconductor device and method of producing the same
A semiconductor device is provided in which a semiconductor substrate can be prevented from being broken while elements can be prevented from being destroyed by...
US-1,006,8997 SiGe heterojunction bipolar transistor with crystalline raised base on germanium etch stop layer
A thin Ge layer is formed between an SiGe intrinsic base and single-crystal Si extrinsic base structures to greatly simplify the fabrication of raised-base SiGe...
US-1,006,8996 Array substrate, fabrication method, and display panel
An array substrate, a fabrication method thereof, and a display panel are provided. The array substrate comprises a substrate, and a plurality of ...
US-1,006,8995 Semiconductor device including field effect transistor and a method for fabricating the same
In a method of fabricating a field effect transistor, a fin structure made of a first semiconductor material is formed so that the fin structure protrudes from...
US-1,006,8994 III-V fin generation by lateral growth on silicon sidewall
A method comprises providing a structure defined by a silicon material on a buried oxide layer of a substrate; causing a nucleation of a III-V material in a...
US-1,006,8993 Semiconductor devices and methods of manufacturing the same
Methods of forming an integrated circuit device are provided. The methods may include forming a gate structure on a substrate, forming a first etch mask on a...
US-1,006,8992 Semiconductor device including fin FET and manufacturing method thereof
A semiconductor device includes a fin structure for a fin field effect transistor (FET). The fin structure includes a base layer protruding from a substrate, an...
US-1,006,8991 Patterned sidewall smoothing using a pre-smoothed inverted tone pattern
Embodiments are directed to a method and resulting structures for smoothing the sidewall roughness of a post-etched film. A sacrificial layer is formed on a...
US-1,006,8990 Method of manufacturing MOS transistor with stack of cascaded nanowires
A MOS transistor with stacked nanowires and a method of manufacturing the same. The transistor may include a stack of cascaded nanowires extending in a first...
US-1,006,8989 Substrate for display device, display device including the substrate, and method of manufacturing the display...
A substrate for a display device is disclosed. In one aspect, the substrate includes an active layer that is formed on substantially the entire portion of the...
US-1,006,8988 Doped poly-silicon for PolyCMP planarity improvement
A method includes forming a polysilicon layer with an uneven upper surface over a first region and a second region of a substrate, doping a top portion of the...
US-1,006,8987 Vertical field effect transistor (VFET) having a self-aligned gate/gate extension structure and method
Disclosed are embodiments of a semiconductor structure that includes a vertical field effect transistor (VFET). The VFET has a fin-shaped body that includes a...
US-1,006,8986 Enhanced-mode high electron mobility transistor and method for forming the same
Embodiments of the disclosure relate to an enhanced-mode high electron mobility transistor. The enhanced-mode high electron mobility transistor includes a...
US-1,006,8985 Method for manufacturing semiconductor substrate, method for manufacturing semiconductor device, semiconductor...
A method for manufacturing a semiconductor substrate, the semiconductor substrate including: a substrate; an initial layer provided on the substrate; a...
US-1,006,8984 Method of manufacturing high-k dielectric using HfO/Ti/Hfo layers
A semiconductor device and method of manufacturing same are described. A first hafnium oxide (HfO.sub.2) layer is formed on a substrate. A titanium (Ti) layer...
US-1,006,8983 High-K metal gate
An integrated circuit containing metal replacement gates may be formed by forming a nitrogen-rich titanium-based barrier between a high-k gate dielectric layer...
US-1,006,8982 Structure and formation method of semiconductor device structure with metal gate
A structure and a formation method of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a...
US-1,006,8981 Rare earth metal surface-activated plasma doping on semiconductor substrates
Methods of doping semiconductor substrates using deposition of a rare earth metal-containing film such as an yttrium-containing film, and annealing techniques...
US-1,006,8980 Vertical fin with a gate structure having a modified gate geometry
A method of forming a gate structure with a modified gate geometry, including, forming two gate spacers and a dummy gate fill on a channel, wherein the dummy...
US-1,006,8979 Planar field effect transistor
A fin-shaped field effect transistor includes a substrate and a gate. The substrate includes an active area, where the active area includes a fin structure...
US-1,006,8978 Methods, apparatus and system for providing source-drain epitaxy layer with lateral over-growth suppression
At least one method, apparatus and system disclosed herein for suppressing over-growth of epitaxial layer formed on fins of fin field effect transistor (finFET)...
US-1,006,8977 Power MOSFET with a deep source contact
A power MOSFET IC device including an array of MOSFET cells formed in a semiconductor substrate. The array of MOSFET cells comprises an interior region of...
US-1,006,8976 Enhancement mode field-effect transistor with a gate dielectric layer recessed on a composite barrier layer for...
An enhancement mode field-effect transistor (E-FET) for high static performance is provided. A composite barrier layer comprises a lower barrier layer and an...
US-1,006,8975 Semiconductor device having field plate structures, source regions and gate electrode structures between the...
A semiconductor device includes a semiconductor substrate having a first surface, first and second field plate structures extending in a first direction...
US-1,006,8974 Field plate power device and method of manufacturing the same
A field plate power device comprises: a substrate; a multilayer semiconductor layer disposed on the substrate; a source electrode, a drain electrode, and a gate...
US-1,006,8973 Doped aluminum nitride crystals and methods of making them
Fabrication of doped AlN crystals and/or AlGaN epitaxial layers with high conductivity and mobility is accomplished by, for example, forming mixed crystals...
US-1,006,8972 Semiconductor device with opposite conductivity-type impurity regions between source and trench gate for...
A semiconductor device is provided with a semiconductor substrate and a trench gate. The semiconductor substrate is provided with a drift region of a first...
US-1,006,8971 Junctionless field-effect transistor having ultra-thin low-crystalline-silicon channel and fabrication method...
A junctionless field-effect transistor is provided and has an ultra-thin low-crystalline silicon channel. A fabrication method thereof also is provided for...
US-1,006,8970 Nanowire isolation scheme to reduce parasitic capacitance
A method for manufacturing a semiconductor device includes forming a doped silicon layer on a bulk substrate, forming an undoped silicon cap layer on the doped...
US-1,006,8969 Nanowire transistor and method for fabricating the same
A method for fabricating a nanowire transistor is disclosed. First, a substrate is provided, and a stack structure is formed on the substrate, in which the...
US-1,006,8968 B.sub.xC.sub.yN.sub.z nanotube formation via the pressurized vapor/condenser method
Nanotube filaments comprising carbon, boron and nitrogen of the general formula B.sub.xC.sub.yN.sub.z, having high-aspect ratio and high-crystallinity produced...
US-1,006,8967 Self-forming spacers using oxidation
A method of forming a self-forming spacer using oxidation. The self-forming spacer may include forming a fin field effect transistor on a substrate, the fin...
US-1,006,8966 Semiconductor channel-stop layer and method of manufacturing the same
A method for manufacturing a semiconductor device may include forming a semiconductor portion, forming a doped portion, and forming a dielectric member. A side...
US-1,006,8965 Lateral high-voltage device
The present invention relates to a lateral high-voltage device. The device includes a dielectric trench region. A doping-overlapping structure with different...
US-1,006,8964 Semiconductor device
A semiconductor device includes a semiconductor layer made of a wide bandgap semiconductor and including a gate trench; a gate insulating film formed on the...
US-1,006,8963 Fin-type field effect transistor and method of forming the same
Provided is a FinFET including a substrate, at least one fin and at least one gate. A portion of the at least one fin is embedded in the substrate. The at least...
US-1,006,8961 Integrated circuit comprising at least an integrated antenna
An integrated circuit on a substrate includes a peripheral portion that surrounds an active area and is positioned close to a scribe line providing separation...
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