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Patent # Description
US-1,006,8910 Non-volatile semiconductor memory device
Provided is a small-area one-time programmable semiconductor memory device that uses a PNPN structure, which is parasitically generated in a CMOS process. An...
US-1,006,8909 Layout pattern of a memory device formed by static random access memory
The present invention provides a layout pattern of a memory device composed of static random access memory (SRAM), comprising four memory units located on a...
US-1,006,8908 Method to form localized relaxed substrate by using condensation
Methods and structures for forming a localized, strained region of a substrate are described. Trenches may be formed at boundaries of a localized region of a...
US-1,006,8907 Dynamic random access memory
A dynamic random access memory (DRAM) includes a substrate, two buried word lines and a bit line contact. The substrate includes a first active area, wherein...
US-1,006,8906 Semiconductor device including oxide semiconductor transistors with low power consumption
The semiconductor device of the present invention comprises first and second transistors and first and second capacitors. One of source and drain electrodes of...
US-1,006,8905 Apparatus for FinFETs
A device comprises a first inverter comprising a first p-type transistor (PU) and a first n-type transistor (PD), a second inverter cross-coupled to the first...
US-1,006,8904 Semiconductor device
A semiconductor device includes first and second active regions and a field insulating film contacting between the first and second active regions, and a gate...
US-1,006,8903 Methods and apparatus for artificial exciton in CMOS processes
Methods and apparatus for artificial exciton devices. An artificial exciton device includes a semiconductor substrate; at least one well region doped to a first...
US-1,006,8902 Integrated circuit structure incorporating non-planar field effect transistors with different channel region...
Disclosed is a method of forming an integrated circuit (IC) structure with multiple non-planar transistors having different effective channel widths. In the...
US-1,006,8901 Semiconductor device including transistors with different threshold voltages
A semiconductor device including a substrate includes a first region and a second region and first and second transistors in the first and second regions,...
US-1,006,8900 Semiconductor device with dummy pattern in high-voltage region and method of forming the same
A semiconductor device includes a substrate having a high-voltage (HV) region; HV gate structures formed in the HV region of the substrate; a HV dummy pattern...
US-1,006,8899 IC structure on two sides of substrate and method of forming
An integrated circuit (IC) structure uses a single semiconductor substrate having a first side and an opposing, second side. A first plurality of active devices...
US-1,006,8898 On-chip MIM capacitor
A method for forming an on-chip capacitor with complementary metal oxide semiconductor (CMOS) devices includes forming a first capacitor electrode between gate...
US-1,006,8897 Shallow trench isolation area having buried capacitor
A method of forming a semiconductor device includes providing a semiconductor substrate including a source/drain region, an active transistor region, and a...
US-1,006,8896 Electrostatic discharge protection device and manufacturing method thereof
An ESD protection device includes a semiconductor substrate, a well, a gate structure, a first source/drain region, a second source/drain region, a first doped...
US-1,006,8895 Transistors patterned with electrostatic discharge protection and methods of fabrication
High-voltage semiconductor devices with electrostatic discharge (ESD) protection and methods of fabrication are provided. The semiconductor devices include a...
US-1,006,8894 Low leakage bidirectional clamps and methods of forming the same
Low leakage bidirectional clamps and methods of forming the same are provided. In certain configurations, a bidirectional clamp includes a first p-well region,...
US-1,006,8893 Diode-based ESD concept for DEMOS protection
The invention relates to an ESD protection circuit for an integrated circuit including a drain-extended MOS device and an output pad that requires protection....
US-1,006,8892 Semiconductor device in a level shifter with electrostatic discharge (ESD) protection circuit and semiconductor...
The present disclosure relates to a semiconductor chip having a level shifter with electro-static discharge (ESD) protection circuit and device applied to...
US-1,006,8891 Semiconductor device
An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second...
US-1,006,8890 Semiconductor device, electronic component, and electronic device
To provide a semiconductor device including element layers that are stacked. A first wiring layer and a second wiring layer are stacked between a first element...
US-1,006,8889 System in package
An electronic system without using solder balls between electrical components, and without using interposer between chips and package substrate, without using a...
US-1,006,8888 Making semiconductor devices with alignment bonding and substrate removal
Embodiments include a manufacturing method of making a semiconductor device via multiple stages of alignment bonding and substrate removal. One example is an...
US-1,006,8887 Semiconductor packages and methods of forming the same
Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a semiconductor package including a first...
US-1,006,8886 Implementing inverted master-slave 3D semiconductor stack
A method and apparatus are provided for implementing an enhanced three dimensional (3D) semiconductor stack. A chip carrier has an aperture of a first length...
US-1,006,8885 Optical apparatus
An optical apparatus includes a substrate 1, a wiring pattern 8 formed on the substrate 1, a light-receiving element 3 and a light-emitting element 2 provided...
US-1,006,8884 Display apparatus and manufacturing method thereof
A display apparatus including a first substrate including a plurality of light emitting diodes regularly disposed thereon, a second substrate including a...
US-1,006,8883 Optical coupling device
An optical coupling device includes a first receiving chip having a first region on one end and a second region on another end side. A first emitting chip is...
US-1,006,8882 High-frequency module
A high-frequency module includes a wiring substrate, a high-frequency circuit including circuit components disposed on the upper surface of the wiring...
US-1,006,8881 Package-on-package type semiconductor package and method of fabricating the same
Provided are a package-on-package type semiconductor package and a method of fabricating the same. The semiconductor package includes upper package stacked on a...
US-1,006,8880 Power module
It is an object of the present invention to provide a power module which can withstand a high voltage with a thin insulating layer. A power module of the...
US-1,006,8879 Three-dimensional stacked integrated circuit devices and methods of assembling the same
An integrated circuit (IC) device is described. The IC device includes a substrate. A connection component including a cavity therethrough is attached to the...
US-1,006,8878 Printed circuit board (PCB), method of manufacturing the PCB, and method of manufacturing semiconductor package...
Provided are a printed circuit board (PCB) capable of blocking introduction of impurities during a molding process so as to reduce damage on a semiconductor...
US-1,006,8877 Semiconductor device and method of forming WLCSP with semiconductor die embedded within interconnect structure
A semiconductor device includes a semiconductor die. An encapsulant is deposited over the semiconductor die. An insulating layer is formed over the encapsulant...
US-1,006,8876 Semiconductor device and manufacturing method therefor
A semiconductor devise includes a first substrate and a second substrate which are bonded each other. A first substrate includes an insulating first surface...
US-1,006,8875 Apparatuses and methods for heat transfer from packaged semiconductor die
Apparatuses and methods for heat transfer from packaged semiconductor die are described. For example, an apparatus may include a plurality of die in a stack,...
US-1,006,8874 Method for direct integration of memory die to logic die without use of thru silicon vias (TSV)
A method including forming a first substrate including an integrated circuit device layer disposed between a plurality of first interconnects and a plurality of...
US-1,006,8873 Method and apparatus for connecting packages onto printed circuit boards
Methods and apparatus are disclosed for attaching the integrated circuit (IC) packages to printed circuit boards (PCBs) to form smooth solder joints. A polymer...
US-1,006,8872 Mounting apparatus and method of correcting offset amount of the same
A method, which includes: a first chip-position calculation step of taking an image of an upper surface of a reference chip and an image of a lower surface of a...
US-1,006,8871 Semiconductor device and method for manufacturing the same
A semiconductor device includes a semiconductor substrate with a wiring layer formed thereon, an insulating film formed on the semiconductor substrate so as to...
US-1,006,8870 Semiconductor device including a connection unit and semiconductor device fabrication method of the same
A semiconductor device includes a plurality of semiconductor units each including a laminated substrate formed by laminating an insulating board and a circuit...
US-1,006,8869 Mounting structure and BGA ball
A mounting structure includes a BGA including a BGA electrode, a circuit board including a circuit board electrode, and a solder joining portion which is...
US-1,006,8868 Multi-strike process for bonding packages and the packages thereof
A method includes performing a first strike process to strike a metal bump of a first package component against a metal pad of a second package component. A...
US-1,006,8867 Post-passivation interconnect structure and methods thereof
A method includes providing a die including a substrate and a bonding pad over the substrate, forming a connective layer over the die, and forming the landing...
US-1,006,8866 Integrated circuit package having rectangular aspect ratio
An integrated circuit (IC) packaging arrangement for surface mounting of the IC includes a package body that encapsulates one or more IC dies. The package body...
US-1,006,8865 Combing bump structure and manufacturing method thereof
A combing bump structure includes a semiconductor substrate, a pad, a conductive layer, a solder bump and at least two metal side walls The pad is disposed on...
US-1,006,8864 Nanowires for pillar interconnects
An embodiment of the invention may include a semiconductor structure, and method of forming the semiconductor structure. The semiconductor structure may include...
US-1,006,8863 Formation of solder and copper interconnect structures and associated techniques and configurations
Embodiments of the present disclosure are directed toward formation of solder and copper interconnect structures and associated techniques and configurations....
US-1,006,8862 Semiconductor device and method of forming a package in-fan out package
A semiconductor device comprises a first semiconductor package including a first interconnect structure extending over a surface of the first semiconductor...
US-1,006,8861 Semiconductor device
Provided is a semiconductor device including a substrate, a pad, a protective layer, a plurality of convex patterns, a redistribution layer (RDL), and a bump....
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