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Patent # Description
US-1,006,8843 Semiconductor device and method of forming cavity in build-up interconnect structure for short signal path...
In a semiconductor device, a first semiconductor die is mounted with its active surface oriented to a temporary carrier. An encapsulant is deposited over the...
US-1,006,8842 Single-layer wiring package substrate, single-layer wiring package structure having the package substrate, and...
A single-layer wiring package substrate and a method of fabricating the same are provided, the method including: forming on a carrier a wiring layer having a...
US-1,006,8841 Apparatus and methods for multi-die packaging
A semiconductor device assembly includes an interposer having an opening extending from a first major surface to a second major surface of the interposer and a...
US-1,006,8840 Electrical interconnect for an integrated circuit package and method of making same
An electrical interconnect assembly for use in an integrated circuit package includes a mounting substrate having a thickness defined between a first surface...
US-1,006,8839 Circuitized substrate with electronic components mounted on transversal portion thereof
A circuitized substrate for mounting at least one electronic component having a plurality of terminals. The circuitized substrate includes a first portion of...
US-1,006,8838 Glass fiber reinforced package substrate
A glass fiber layer is embedded in a thin film package substrate to reinforce the strength of the thin film package substrate. The thin film package substrate...
US-1,006,8837 Universal preformed lead frame device
A universal preformed lead frame device includes a plurality of spaced-apart longitudinal and transverse sections, and a plurality of preformed lead frame units...
US-1,006,8836 Metal gate transistor, integrated circuits, systems, and fabrication methods thereof
An integrated circuit includes a substrate, a first inter-layer dielectric (ILD) layer over the substrate, and a gate strip having a first width formed in the...
US-1,006,8835 Process flow for a combined CA and TSV oxide deposition
A method of forming a TSV isolation layer and a transistor-to-BEOL isolation layer during a single deposition process and the resulting device are disclosed....
US-1,006,8834 Floating bond pad for power semiconductor devices
Embodiments of a semiconductor device including a floating bond pad are disclosed. In one preferred embodiment, the semiconductor device is a power...
US-1,006,8833 Heat module
A heat module includes a fan, a heat sink, a heat transfer member, and a plurality of connection portions. The heat transfer member includes a lower surface...
US-1,006,8832 EMI shielding structure having heat dissipation unit and method for manufacturing the same
An electromagnetic interference shielding structure is disclosed. The electromagnetic interference shielding structure includes an insulating member covering at...
US-1,006,8831 Thermally enhanced semiconductor package and process for making the same
The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the module...
US-1,006,8830 Compressible thermal interface materials
Provided is a compressible thermal interface material including a polymer, a thermally conductive filler, and a phase change material. A formulation for forming...
US-1,006,8829 Power-module substrate unit and power module
A power-module substrate unit having at least one power-module substrate including one ceramic substrate, a circuit layer formed on one surface of the ceramic...
US-1,006,8828 Semiconductor storage devices
A semiconductor storage device includes a circuit substrate. The circuit substrate includes a main body and a connection tab connected to a side of the main...
US-1,006,8827 Integrated circuit heat dissipation using nanostructures
An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature...
US-1,006,8826 Package device
Provided is a package device, relating to the technical field of lamp beads. The package device comprises an SMD holder, wherein the SMD holder is a hollow...
US-1,006,8825 Semiconductor device
A semiconductor device includes: a semiconductor element which includes semiconductor substrate, an insulating film formed on a front surface of the...
US-1,006,8824 Electronic component package having electronic component within a frame on a redistribution layer
An electronic component package includes a frame, an electronic component, an encapsulant, a metal layer, and a redistribution layer. The frame has a through...
US-1,006,8823 Semiconductor device
A semiconductor device suitable for preventing malfunction is provided. The semiconductor device includes a semiconductor chip 1, a first electrode pad 21...
US-1,006,8822 Semiconductor package and method for forming the same
A method for forming semiconductor packages includes disposing at least one flow hindering supporter onto a substrate, in which the substrate has at least one...
US-1,006,8821 Semiconductor component support and semiconductor device
A semiconductor component support is provided which includes a component support portion for a semiconductor component to be mounted on the semiconductor...
US-1,006,8820 Electronic element package and method for manufacturing the same
The present disclosure relates to an electronic element package and a method of manufacturing the same. The electronic element package includes a substrate, an...
US-1,006,8819 Semiconductor device
A relay substrate in which a circuit pattern and an external electrode are integrated on a insulating plate is used in the semiconductor device. Such...
US-1,006,8818 Semiconductor element package, semiconductor device, and mounting structure
A semiconductor element package includes a base body, a frame member, and a terminal member. The frame member is provided on a main surface of the base body. A...
US-1,006,8817 Semiconductor package
A semiconductor package and die assembly with a package having an exterior surface and an interior space, the interior space defined by a first side wall, and a...
US-1,006,8816 Scan cell coupled to via ends, buffer coupled to via
The disclosure describes a novel method and apparatus for testing different types of TSVs in a single die or different types of TSV connections in a stack of...
US-1,006,8815 Test structure for testing via resistance and method
Aspects of the present disclosure include a semiconductor test device and method. The test device includes a first Kelvin testable structure and a second Kelvin...
US-1,006,8814 Apparatus and method for evaluating semiconductor device comprising thermal image processing
An apparatus for evaluating a semiconductor device includes: a chuck stage for fixing a semiconductor device; an insulating substrate; a plurality of probes...
US-1,006,8813 Array substrate, liquid crystal display panel and broken-line repairing method thereof
According to the present disclosure, there is disclosed an array substrate, a liquid crystal display panel and a broken-line repairing method thereof. The array...
US-1,006,8812 Method and structure for flip-chip package reliability monitoring using capacitive sensors groups
Flip-chip package reliability monitoring and systems of monitoring using capacitive sensors are disclosed. The monitoring is conducted in situ and in real-time...
US-1,006,8811 Method of evaluating gettering property
A gettering property evaluating method for a wafer includes: a gettering layer forming step of polishing a back surface opposite to a front surface of a...
US-1,006,8810 Multiple Fin heights with dielectric isolation
A method of forming semiconductor fins having different fin heights and which are dielectrically isolated from an underlying semiconductor substrate. The fins...
US-1,006,8809 TFT backplane manufacturing method and TFT backplane
The invention provides a manufacturing method for TFT backplane, through forming an oxygen-containing a-Si layer on the buffer layer and an oxygen-free a-Si...
US-1,006,8808 Semiconductor device and method for fabricating the same
A semiconductor device includes: a fin-shaped structure on a substrate, in which the fin-shaped structure includes a top portion and a bottom portion; a doped...
US-1,006,8807 Uniform shallow trench isolation
A method for forming a field-effect transistor (FET) including forming a plurality of individual fins on a substrate. The method continues with forming a dummy...
US-1,006,8806 Method, apparatus, and system for using a cover mask for enabling metal line jumping over MOL features in a...
At least one method, apparatus and system disclosed involves providing an integrated circuit having metal feature flyover over an middle-of-line (MOL) feature....
US-1,006,8805 Self-aligned spacer for cut-last transistor fabrication
Semiconductor devices include one or more semiconductor fins. A gate is formed over the one or more semiconductor fins. A vertical sidewall is formed at a...
US-1,006,8804 Methods, apparatus and system for providing adjustable fin height for a FinFET device
A method and system are disclosed herein for an adjustable effective fin height in a gate region of a finFET device. Fin structures, each having a first height,...
US-1,006,8803 Planarization process
A planarization process is disclosed. The method includes forming a trench in an area of a material layer which has a relatively high loading condition for...
US-1,006,8802 Threshold mismatch and IDDQ reduction using split carbon co-implantation
An integrated circuit containing MOS transistors may be formed using a split carbon co-implantation. The split carbon co-implant includes an angled carbon...
US-1,006,8801 Substrate dividing method
A substrate dividing method which can thin and divide a substrate while preventing chipping and cracking from occurring. This substrate dividing method...
US-1,006,8800 Manufacturing method for solid-state imaging device and solid-state imaging device
A method for manufacturing a solid-state imaging device comprises a first step of preparing an imaging element having a second principal surface having an...
US-1,006,8799 Self-aligned contact
A semiconductor device includes a gate structure having a gate conductor and a sidewall spacer. A partial dielectric cap is formed on the gate conductor and...
US-1,006,8798 Method and processing apparatus for performing pre-treatment to form copper wiring in recess formed in substrate
There is provided a method for performing a pre-treatment to form a copper wiring in a recess formed in a substrate, which includes forming a barrier layer on a...
US-1,006,8797 Semiconductor process for forming plug
A semiconductor process for forming a plug includes the following steps. A dielectric layer having a recess is formed on a substrate. A titanium layer is formed...
US-1,006,8796 Semiconductor device manufacturing method
A semiconductor device manufacturing method includes forming a first hole in a first processed layer. A first sacrificial film is formed in the first hole. A...
US-1,006,8795 Methods for preparing layered semiconductor structures
Methods for preparing layered semiconductor structures are disclosed. The methods may involve pretreating an ion-implanted donor wafer by annealing the...
US-1,006,8794 Gate all around device architecture with hybrid wafer bond technique
A system and method for fabricating non-planar devices while managing semiconductor processing yield and cost are described. A semiconductor device fabrication...
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