Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching:





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
US-1,006,8810 Multiple Fin heights with dielectric isolation
A method of forming semiconductor fins having different fin heights and which are dielectrically isolated from an underlying semiconductor substrate. The fins...
US-1,006,8809 TFT backplane manufacturing method and TFT backplane
The invention provides a manufacturing method for TFT backplane, through forming an oxygen-containing a-Si layer on the buffer layer and an oxygen-free a-Si...
US-1,006,8808 Semiconductor device and method for fabricating the same
A semiconductor device includes: a fin-shaped structure on a substrate, in which the fin-shaped structure includes a top portion and a bottom portion; a doped...
US-1,006,8807 Uniform shallow trench isolation
A method for forming a field-effect transistor (FET) including forming a plurality of individual fins on a substrate. The method continues with forming a dummy...
US-1,006,8806 Method, apparatus, and system for using a cover mask for enabling metal line jumping over MOL features in a...
At least one method, apparatus and system disclosed involves providing an integrated circuit having metal feature flyover over an middle-of-line (MOL) feature....
US-1,006,8805 Self-aligned spacer for cut-last transistor fabrication
Semiconductor devices include one or more semiconductor fins. A gate is formed over the one or more semiconductor fins. A vertical sidewall is formed at a...
US-1,006,8804 Methods, apparatus and system for providing adjustable fin height for a FinFET device
A method and system are disclosed herein for an adjustable effective fin height in a gate region of a finFET device. Fin structures, each having a first height,...
US-1,006,8803 Planarization process
A planarization process is disclosed. The method includes forming a trench in an area of a material layer which has a relatively high loading condition for...
US-1,006,8802 Threshold mismatch and IDDQ reduction using split carbon co-implantation
An integrated circuit containing MOS transistors may be formed using a split carbon co-implantation. The split carbon co-implant includes an angled carbon...
US-1,006,8801 Substrate dividing method
A substrate dividing method which can thin and divide a substrate while preventing chipping and cracking from occurring. This substrate dividing method...
US-1,006,8800 Manufacturing method for solid-state imaging device and solid-state imaging device
A method for manufacturing a solid-state imaging device comprises a first step of preparing an imaging element having a second principal surface having an...
US-1,006,8799 Self-aligned contact
A semiconductor device includes a gate structure having a gate conductor and a sidewall spacer. A partial dielectric cap is formed on the gate conductor and...
US-1,006,8798 Method and processing apparatus for performing pre-treatment to form copper wiring in recess formed in substrate
There is provided a method for performing a pre-treatment to form a copper wiring in a recess formed in a substrate, which includes forming a barrier layer on a...
US-1,006,8797 Semiconductor process for forming plug
A semiconductor process for forming a plug includes the following steps. A dielectric layer having a recess is formed on a substrate. A titanium layer is formed...
US-1,006,8796 Semiconductor device manufacturing method
A semiconductor device manufacturing method includes forming a first hole in a first processed layer. A first sacrificial film is formed in the first hole. A...
US-1,006,8795 Methods for preparing layered semiconductor structures
Methods for preparing layered semiconductor structures are disclosed. The methods may involve pretreating an ion-implanted donor wafer by annealing the...
US-1,006,8794 Gate all around device architecture with hybrid wafer bond technique
A system and method for fabricating non-planar devices while managing semiconductor processing yield and cost are described. A semiconductor device fabrication...
US-1,006,8793 Semiconductor structure for preventing generation of void and method for manufacturing the same
A semiconductor structure including a substrate, an isolation structure, a first gate structure, a second gate structure and a protection layer is provided. The...
US-1,006,8792 Method and apparatus for liquid treatment of wafer shaped articles
An apparatus for processing wafer-shaped articles comprises a rotary chuck adapted to hold a wafer shaped article thereon. The rotary chuck comprises a...
US-1,006,8791 Wafer susceptor for forming a semiconductor device and method therefor
In one embodiment, a wafer susceptor is formed to have portion of the susceptor that is positioned between a wafer pocket and an outside edge of the susceptor...
US-1,006,8790 Electrostatic chuck device
An electrostatic chuck device that adsorbs a plate-like specimen with an electrostatic adsorption electrode and cools the plate-like specimen, including an...
US-1,006,8789 Method of using a wafer cassette to charge an electrostatic carrier
A method comprising placing a wafer assembly in a wafer cassette, wherein the wafer assembly includes a wafer and an electrostatic carrier attached to the...
US-1,006,8788 Communication device and method for controlling communication device
A communication device includes a communicator that performs communication via a network, IO ports that connect with a manufacturing apparatus, a packet monitor...
US-1,006,8787 Bowing semiconductor wafers
Methods for processing semiconductor wafers, methods for loading semiconductor wafers into wafer carriers, and semiconductor wafer carriers. The methods and...
US-1,006,8786 Data structures for semiconductor die packaging
At least some embodiments are directed to a system that comprises storage comprising a data structure that cross-references an identifier of a semiconductor...
US-1,006,8785 Wafer loading apparatus of wafer polishing equipment and method for adjusting wafer loading position
An embodiment relates to a wafer loading apparatus of wafer polishing equipment. Provided is the wafer loading apparatus of wafer polishing equipment,...
US-1,006,8784 Indicator used in electronic device manufacturing apparatus and method for designing and/or managing the apparatus
Provided is an indicator that can easily detect whether treatment with at least one member of plasma, ozone, ultraviolet rays, and radical-containing gas is...
US-1,006,8783 Sample holder
A sample holder of the present invention includes a base body formed of ceramic substrates laminated to each other and having an upper surface functioning as a...
US-1,006,8782 Device and method for scribing a bottom-side of a substrate while viewing the top side
A device includes a table surface defining a horizontal plane having an x-axis and a y-axis orthogonal to the x-axis and the x-axis and y-axis lie in the...
US-1,006,8781 Systems and methods for drying high aspect ratio structures without collapse using sacrificial bracing material...
Systems and methods for drying a substrate including a plurality of high aspect ratio (HAR) structures are performed after at least one of wet etching and/or...
US-1,006,8780 Lead frame connected with heterojunction semiconductor body
A semiconductor component includes a semiconductor chip including a first semiconductor body comprising silicon and a second semiconductor body attached to an...
US-1,006,8779 Systems and methods for fabricating a polycrystaline semiconductor resistor on a semiconductor substrate
In accordance with embodiments of the present disclosure, an integrated circuit may include at least one region of shallow-trench isolation field oxide, at...
US-1,006,8778 Plasma processing method and plasma processing apparatus
This plasma processing method includes a film formation step, a plasma processing step and a removal step. In the film formation step, a silicon oxide film is...
US-1,006,8776 Raster-planarized substrate interlayers and methods of planarizing same
An interlayer dielectric material includes a planar surface that exhibits planarity due to raster-patterned decomposition products due to use of a confocal...
US-1,006,8775 Method of bonding supporting substrate with device substrate for fabricating semiconductor device
According to one embodiment, a method for fabricating a semiconductor device is provided. The method for fabricating the semiconductor device includes three...
US-1,006,8774 Semiconductor device and manufacturing method thereof
A method of manufacturing a source structure for a p-type metal-oxide-semiconductor (PMOS) field effect transistor (FET) is provided. In the method, a first...
US-1,006,8773 Contact formation for split gate flash memory
An integrated circuit structure includes a plurality of flash memory cells forming a memory array, wherein each of the plurality of flash memory cells includes...
US-1,006,8772 Recess channel semiconductor non-volatile memory device and fabricating the same
A recess channel semiconductor non-volatile memory (NVM) device is disclosed. The recess channel MOSFET devices by etching into the silicon substrate for the...
US-1,006,8771 System and method for mitigating oxide growth in a gate dielectric
Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in...
US-1,006,8770 Method and structure for semiconductor device having gate spacer protection layer
A method of forming a semiconductor device includes providing a precursor. The precursor includes a substrate; a gate stack over the substrate; a first...
US-1,006,8769 Methods and apparatus for preventing counter-doping during high temperature processing
In a described example method, semiconductor wafer with a backside silicon nitride layer is encapsulated with a diffusion barrier layer prior to a high...
US-1,006,8768 Semiconductor device including line patterns
Provided is a semiconductor device. The device includes a plurality of line patterns, which extend in a first direction and are arranged a first space apart...
US-1,006,8767 Method of fabricating semiconductor device
A method for fabricating a semiconductor device includes forming a first mask pattern on a first film to extend in a first direction, forming a first spacer on...
US-1,006,8766 Oxidizing and etching of material lines for use in increasing or decreasing critical dimensions of hard mask lines
A method includes, for example, providing a starting semiconductor structure having a plurality of material lines disposed over a hard mask, and the hard mask...
US-1,006,8765 Multi-step system and method for curing a dielectric film
A multi-step system and method for curing a dielectric film in which the system includes a drying system configured to reduce the amount of contaminants, such...
US-1,006,8764 Selective metal oxide deposition using a self-assembled monolayer surface pretreatment
Embodiments of the invention provide methods for selective film deposition using a surface pretreatment. According to one embodiment, the method includes...
US-1,006,8763 Coating film forming method, coating film forming apparatus, and storage medium
A method of forming a coating film includes horizontally supporting a substrate, supplying a coating solution to a central portion of the substrate and...
US-1,006,8762 Manufacture method of gate insulating film for silicon carbide semiconductor device
Providing a manufacture method of a gate insulating film formed on an SiC substrate having thereon an SiON film, achieving both of the maintenance of an SiON...
US-1,006,8761 Fast modulation with downstream homogenisation
A method of mass spectrometry is disclosed involving scanning a parameter of a first device through which a mixture of components is passed. Different...
US-1,006,8760 MALDI-TOF mass spectrometers with delay time variations and related methods
MALDI-TOF MS systems have solid state lasers and successive and varied delay times between ionization and acceleration (e.g. extraction) to change focus masses...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.