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Patent # Description
US-1,007,4651 Semiconductor device having transistors formed by double patterning and manufacturing method therefor
A semiconductor device is provided which suppresses variations in transistor characteristics such as a source-drain diffusion capacitance. A first transistor...
US-1,007,4650 Deep trench isolation for RF devices on SOI
A semiconductor device includes a silicon-on-insulator (SOI) substrate having a stack of a first semiconductor substrate, a buried insulating layer and a second...
US-1,007,4649 High-sensitivity electronic detector
An integrated electronic detector operates to detecting a variation in potential on an input terminal. The detector includes a MOS transistor having a drain...
US-1,007,4648 Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device includes: implanting charged particles into a first range and a second range in a semiconductor substrate from...
US-1,007,4647 ESD protection circuit for providing cross-domain ESD protection
A semiconductor device and method. The device includes a first domain and a second domain each having a power rail and a ground rail. The device further...
US-1,007,4646 Display device
A protective circuit includes a non-linear element, which further includes a gate electrode, a gate insulating layer covering the gate electrode, a pair of...
US-1,007,4645 LED module and method of manufacturing the same
A compact LED module and a method of manufacturing such an LED module are provided. The LED module includes a first-pole first lead, a first-pole second lead, a...
US-1,007,4644 Integrated semiconductor device having isolation structure for reducing noise
An integrated semiconductor device includes a first transistor and a second transistor formed on a semiconductor substrate, and an isolation structure located...
US-1,007,4643 Integrated circuit with protection from transient electrical stress events and method therefor
An integrated circuit with protection against transient electrical stress events includes a trigger circuit having a first detection circuit coupled to a first...
US-1,007,4642 Crowbar device for voltage transient circuit protection
A circuit protection component including a crowbar device for protecting electronic devices from transients is generally disclosed. The circuit protection...
US-1,007,4641 Power gating for three dimensional integrated circuits (3DIC)
Embodiments of mechanisms for forming power gating cells and virtual power circuits on multiple active device layers are described in the current disclosure....
US-1,007,4640 Integrated circuit cell library for multiple patterning
A method is disclosed for defining a multiple patterned cell layout for use in an integrated circuit design. A layout is defined for a level of a cell in...
US-1,007,4639 Isolator integrated circuits with package structure cavity and fabrication methods
Disclosed examples include integrated circuits with a leadframe structure, a first circuit structure including a light source configured to generate a light...
US-1,007,4638 Light emitting device
A light emitting device includes a package having a recess which includes a bottom surface. A first bottom surface of a first light emitting element is put on a...
US-1,007,4637 Structure and formation method for chip package
Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a package layer partially or completely...
US-1,007,4636 LED module and method for fabricating the same
Disclosed is a method for fabricating an LED module. The method includes: constructing a chip-on-carrier including a chip retainer having a horizontal bonding...
US-1,007,4635 Solid state light emitter devices and methods
Solid state light emitter devices and methods are provided. A solid state light emitter device can include a submount having an upper surface and a bottom...
US-1,007,4634 Semiconductor device comprising PN junction diode and schottky barrier diode
A semiconductor device includes a MOSFET including a PN junction diode. A unipolar device is connected in parallel to the MOSFET and has two terminals. A first...
US-1,007,4633 Semiconductor die assemblies having molded underfill structures and related technology
A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies and a package substrate...
US-1,007,4632 Solid-state drive
A solid-state drive (SSD) includes a main printed circuit board (PCB), and a first semiconductor package and a second semiconductor package respectively mounted...
US-1,007,4631 Packages and packaging methods for semiconductor devices, and packaged semiconductor devices
Packages and packaging methods for semiconductor devices, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor...
US-1,007,4630 Semiconductor package with high routing density patch
Methods and systems for a semiconductor package with high routing density routing patch are disclosed and may include a semiconductor die bonded to a substrate...
US-1,007,4629 System on integrated chips and methods of forming same
An embodiment method for forming a semiconductor package includes attaching a first die to a first carrier, depositing a first isolation material around the...
US-1,007,4628 System-in-package and fabrication method thereof
A system-in-package (SiP) includes a RDL structure having a first side and a second side opposite to the first side; a first semiconductor die mounted on the...
US-1,007,4627 Adhesive bonding composition and electronic components prepared from the same
A polymerizable composition includes at least one monomer, a photoinitiator capable of initiating polymerization of the monomer when exposed to light, and a...
US-1,007,4626 Wafer laminate and making method
A wafer laminate has an adhesive layer (2) sandwiched between a support (1) and a wafer (3), with a circuit-forming surface of the wafer facing the adhesive...
US-1,007,4625 Wafer level package (WLP) ball support using cavity structure
An integrated circuit device in a wafer level package (WLP) includes ball grid array (BGA) balls fabricated with cavities filled with adhesives for improved...
US-1,007,4624 Bond pads with differently sized openings
Integrated circuit dies are provide with a passivation layer having a plurality of differently sized openings exposing bond pads for bonding. The sizes of the...
US-1,007,4623 Method of fabricating redistribution circuit structure
A redistribution circuit structure electrically connected to at least one conductor underneath is provided. The redistribution circuit structure includes a...
US-1,007,4622 Semiconductor package device and method of manufacturing the same
A semiconductor package device includes a substrate, a first package body, a permeable element and a coil. The substrate includes a first surface. The first...
US-1,007,4621 Electronic package with antenna structure
Provided is an electronic package, including: a carrier, an electronic component disposed on the carrier, and an antenna structure, wherein the antenna...
US-1,007,4620 Semiconductor package with integrated output inductor using conductive clips
A semiconductor package includes a semiconductor die having a control transistor and a sync transistor, an integrated output inductor having a winding around a...
US-1,007,4619 Optoelectronic component device and method for producing an optoelectronic component device
An optoelectronic component device includes first and second electrodes; a first optoelectronic component electrically coupled to the first and second...
US-1,007,4618 Semiconductor structure and manufacturing method thereof
A semiconductor structure includes a die including a first surface and a second surface opposite to the first surface; a first interconnect structure disposed...
US-1,007,4617 Wafer level package (WLP) and method for forming the same
A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a conductive pad...
US-1,007,4616 Chip protection envelope and method
In an embodiment, a chip protection envelope includes a first dielectric layer including at least one organic component having a decomposition temperature of at...
US-1,007,4615 Package structure and method of fabricating the same
A package structure including at least one conductive plate, a redistribution layer, a first semiconductor chip, a conductive shielding structure and an...
US-1,007,4614 EMI/RFI shielding for semiconductor device packages
An encapsulated semiconductor device package with an overlying conductive EMI or RFI shield in contact with an end of a grounded conductive component at a...
US-1,007,4613 Method of fabricating semiconductor package including cutting encapsulating body and carrier to form packages
A semiconductor package is provided, including: a substrate having opposing first and second surfaces; a plurality of semiconductor components disposed on and...
US-1,007,4612 Method for forming alignment marks and structure of same
A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are...
US-1,007,4611 Semiconductor device and method of forming backside openings for an ultra-thin semiconductor die
A semiconductor substrate contains a plurality of openings extending partially into a surface of the semiconductor substrate. A conductive layer is formed with...
US-1,007,4610 Field-effect transistor, method of manufacturing the same, and radio-frequency device
There is provided a field-effect transistor including: a gate electrode; a semiconductor layer having a source region and a drain region with the gate electrode...
US-1,007,4609 Layout construction for addressing electromigration
A first interconnect on an interconnect level connects a first subset of PMOS drains together of a CMOS device. A second interconnect on the interconnect level...
US-1,007,4608 Method for manufacturing a contact bump by thermal expansion of a patterned sacrificial layer underneath a...
A method for manufacturing metal structures for the electrical connection of components comprises the following steps: depositing an auxiliary layer on a...
US-1,007,4607 Semiconductor device structure with graphene layer
A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and an interconnect...
US-1,007,4606 Via, trench or contact structure in the metallization, prematallization dielectric or interlevel dielectric...
A semiconductor substrate includes a doped region. A premetallization dielectric layer extends over the semiconductor substrate. A first metallization layer is...
US-1,007,4605 Memory cell and array structure having a plurality of bit lines
Provided is a memory device including an array of memory cells. A first bit-line coupled to memory cells of a first column of the array of memory cells. The...
US-1,007,4604 Integrated fan-out package and method of fabricating the same
A method of fabricating an integrated fan-out package is provided. The method includes the followings. An integrated circuit component is mounted on a carrier....
US-1,007,4603 Methods of forming a semiconductor device comprising first and second nitride layers
A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well...
US-1,007,4602 Substrate, semiconductor package structure and manufacturing process
A substrate includes a first conductive structure, a second conductive structure attached to the first conductive structure and a third conductive structure...
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