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Patent # Description
US-1,007,4634 Semiconductor device comprising PN junction diode and schottky barrier diode
A semiconductor device includes a MOSFET including a PN junction diode. A unipolar device is connected in parallel to the MOSFET and has two terminals. A first...
US-1,007,4633 Semiconductor die assemblies having molded underfill structures and related technology
A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies and a package substrate...
US-1,007,4632 Solid-state drive
A solid-state drive (SSD) includes a main printed circuit board (PCB), and a first semiconductor package and a second semiconductor package respectively mounted...
US-1,007,4631 Packages and packaging methods for semiconductor devices, and packaged semiconductor devices
Packages and packaging methods for semiconductor devices, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor...
US-1,007,4630 Semiconductor package with high routing density patch
Methods and systems for a semiconductor package with high routing density routing patch are disclosed and may include a semiconductor die bonded to a substrate...
US-1,007,4629 System on integrated chips and methods of forming same
An embodiment method for forming a semiconductor package includes attaching a first die to a first carrier, depositing a first isolation material around the...
US-1,007,4628 System-in-package and fabrication method thereof
A system-in-package (SiP) includes a RDL structure having a first side and a second side opposite to the first side; a first semiconductor die mounted on the...
US-1,007,4627 Adhesive bonding composition and electronic components prepared from the same
A polymerizable composition includes at least one monomer, a photoinitiator capable of initiating polymerization of the monomer when exposed to light, and a...
US-1,007,4626 Wafer laminate and making method
A wafer laminate has an adhesive layer (2) sandwiched between a support (1) and a wafer (3), with a circuit-forming surface of the wafer facing the adhesive...
US-1,007,4625 Wafer level package (WLP) ball support using cavity structure
An integrated circuit device in a wafer level package (WLP) includes ball grid array (BGA) balls fabricated with cavities filled with adhesives for improved...
US-1,007,4624 Bond pads with differently sized openings
Integrated circuit dies are provide with a passivation layer having a plurality of differently sized openings exposing bond pads for bonding. The sizes of the...
US-1,007,4622 Semiconductor package device and method of manufacturing the same
A semiconductor package device includes a substrate, a first package body, a permeable element and a coil. The substrate includes a first surface. The first...
US-1,007,4621 Electronic package with antenna structure
Provided is an electronic package, including: a carrier, an electronic component disposed on the carrier, and an antenna structure, wherein the antenna...
US-1,007,4620 Semiconductor package with integrated output inductor using conductive clips
A semiconductor package includes a semiconductor die having a control transistor and a sync transistor, an integrated output inductor having a winding around a...
US-1,007,4619 Optoelectronic component device and method for producing an optoelectronic component device
An optoelectronic component device includes first and second electrodes; a first optoelectronic component electrically coupled to the first and second...
US-1,007,4618 Semiconductor structure and manufacturing method thereof
A semiconductor structure includes a die including a first surface and a second surface opposite to the first surface; a first interconnect structure disposed...
US-1,007,4617 Wafer level package (WLP) and method for forming the same
A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a conductive pad...
US-1,007,4616 Chip protection envelope and method
In an embodiment, a chip protection envelope includes a first dielectric layer including at least one organic component having a decomposition temperature of at...
US-1,007,4615 Package structure and method of fabricating the same
A package structure including at least one conductive plate, a redistribution layer, a first semiconductor chip, a conductive shielding structure and an...
US-1,007,4614 EMI/RFI shielding for semiconductor device packages
An encapsulated semiconductor device package with an overlying conductive EMI or RFI shield in contact with an end of a grounded conductive component at a...
US-1,007,4613 Method of fabricating semiconductor package including cutting encapsulating body and carrier to form packages
A semiconductor package is provided, including: a substrate having opposing first and second surfaces; a plurality of semiconductor components disposed on and...
US-1,007,4612 Method for forming alignment marks and structure of same
A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are...
US-1,007,4611 Semiconductor device and method of forming backside openings for an ultra-thin semiconductor die
A semiconductor substrate contains a plurality of openings extending partially into a surface of the semiconductor substrate. A conductive layer is formed with...
US-1,007,4610 Field-effect transistor, method of manufacturing the same, and radio-frequency device
There is provided a field-effect transistor including: a gate electrode; a semiconductor layer having a source region and a drain region with the gate electrode...
US-1,007,4609 Layout construction for addressing electromigration
A first interconnect on an interconnect level connects a first subset of PMOS drains together of a CMOS device. A second interconnect on the interconnect level...
US-1,007,4608 Method for manufacturing a contact bump by thermal expansion of a patterned sacrificial layer underneath a...
A method for manufacturing metal structures for the electrical connection of components comprises the following steps: depositing an auxiliary layer on a...
US-1,007,4607 Semiconductor device structure with graphene layer
A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and an interconnect...
US-1,007,4606 Via, trench or contact structure in the metallization, prematallization dielectric or interlevel dielectric...
A semiconductor substrate includes a doped region. A premetallization dielectric layer extends over the semiconductor substrate. A first metallization layer is...
US-1,007,4605 Memory cell and array structure having a plurality of bit lines
Provided is a memory device including an array of memory cells. A first bit-line coupled to memory cells of a first column of the array of memory cells. The...
US-1,007,4604 Integrated fan-out package and method of fabricating the same
A method of fabricating an integrated fan-out package is provided. The method includes the followings. An integrated circuit component is mounted on a carrier....
US-1,007,4603 Methods of forming a semiconductor device comprising first and second nitride layers
A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well...
US-1,007,4602 Substrate, semiconductor package structure and manufacturing process
A substrate includes a first conductive structure, a second conductive structure attached to the first conductive structure and a third conductive structure...
US-1,007,4601 Wiring substrate and semiconductor device
A wiring substrate includes a first wiring layer, an insulative resin first insulation layer covering the first wiring layer, and a second wiring layer located...
US-1,007,4600 Method of manufacturing interposer-based damping resistor
Various resistor circuits and methods of making and using the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a...
US-1,007,4599 Semiconductor dies with recesses, associated leadframes, and associated systems and methods
Semiconductor dies with recesses, associated leadframes, and associated systems and methods are disclosed. A semiconductor system in accordance with one...
US-1,007,4598 Semiconductor device and manufacturing method thereof
A lead frame includes a plurality of circuit patterns which each have a die pad and an electrode terminal portion and are disposed in a band shape, a tie bar, a...
US-1,007,4597 Interdigit device on leadframe for evenly distributed current flow
The disclosure is directed to techniques to evenly distribute current in interdigited leadframes by decoupling current between interdigited pads. The leadframe...
US-1,007,4596 Method of fabricating a lead frame by additive process
An electronic component, such as an integrated circuit, includes at least one circuit having coupled therewith electrical connections including a lead frame of...
US-1,007,4595 Self-alignment for redistribution layer
An apparatus comprising a substrate with multiple electronic devices. An interconnect structure formed on a first side of the substrate interconnects the...
US-1,007,4594 Semiconductor structure and manufacturing method thereof
A semiconductor structure includes a substrate including a first side, a second side opposite to the first side, and a device layer over the second side, and a...
US-1,007,4593 Shunt resistor integrated in a connection lug of a semiconductor module and method for determining a current...
A semiconductor module includes a housing, a circuit carrier having an insulation carrier and a metallization layer applied to a side of the insulation carrier,...
US-1,007,4592 Pedestal surface for MOSFET module
An electronic package connectable to an electric machine includes a cooling tower having a metallic wall with a radially outer wall surface. The radially outer...
US-1,007,4591 System with provision of a thermal interface to a printed circuit board
Embodiments of the present disclosure provide techniques and configurations for providing a thermal interface to a PCB. In some embodiments, the system for...
US-1,007,4590 Molded package with chip carrier comprising brazed electrically conductive layers
A package which comprises a chip carrier, at least one electronic chip mounted on the chip carrier, an electrically conductive contact structure electrically...
US-1,007,4589 Embedding diamond and other ceramic media into metal substrates to form thermal interface materials
A multi-layer structure includes a substrate with a surface and with particles partially covering and partially embedded in the surface. The particles have high...
US-1,007,4588 Semiconductor devices with a thermally conductive layer and methods of their fabrication
An embodiment of a semiconductor device includes a semiconductor substrate that includes a host substrate and an upper surface, an active area, a substrate...
US-1,007,4587 Bonding wire-type heat sink structure for semiconductor devices
The present invention discloses a bonding-wire-type heat sink structure for semiconductor devices. An embodiment of the said bonding-wire-type heat sink...
US-1,007,4586 Thermal dissipation device and semiconductor package device including the same
A thermal dissipation device includes a main body and a support member. The main body has an upper surface, a lower surface opposite to the upper surface, and a...
US-1,007,4585 Power module with dummy terminal structure
A power module includes a connection terminal for external connection, the connection terminal protruding from the side surface of a package, and a dummy...
US-1,007,4584 Method of forming a semiconductor component comprising a second passivation layer having a first opening...
A conductive feature on a semiconductor component is disclosed. A first passivation layer is formed over a substrate. A bond pad is formed over the first...
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