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Patent # Description
US-1,007,4583 Circuit module and manufacturing method thereof
There is provided a circuit module where a sufficient amount of underfill resin may be supplied to corner portions of a semiconductor chip. A circuit module...
US-1,007,4582 Sealing sheet
Provided is a sealing sheet capable of preventing void and filler segregation from occurring when forming a sealing body in which semiconductor chips are buried...
US-1,007,4581 Chip package having a patterned conducting plate and a conducting pad with a recess
A chip package includes a patterned conducting plate having a plurality of conducting sections electrically separated from each other, a plurality of conducting...
US-1,007,4580 Method to use on-chip temperature sensors for detection of Trojan circuits
A method for detecting a malicious circuit on an integrated circuit chip is provided, in which temperature sensors are thermally coupled to primary circuitry on...
US-1,007,4579 Stacked semiconductor device
A stacked semiconductor device may include: a base die; and a plurality of core dies stacked over the base die, and suitable for communicating with allocated...
US-1,007,4578 Semiconductor device and method for producing the same
Provided is a semiconductor device capable of measuring a depth of removal of a silicon carbide (SiC) wafer with high accuracy through simple steps, and a...
US-1,007,4577 Silicon germanium and silicon fins on oxide from bulk wafer
A method for forming fins includes growing a SiGe layer and a silicon layer over a surface of a bulk Si substrate, patterning fin structures from the silicon...
US-1,007,4576 Semiconductor memory device
A semiconductor device including a circuit that has a reduced area is provided. Alternatively, a semiconductor device including a circuit that can have a...
US-1,007,4575 Integrating and isolating nFET and pFET nanosheet transistors on a substrate
Embodiments of the invention are directed to methods of fabricating nanosheet channel field effect transistors. An example method includes forming a first...
US-1,007,4574 Integrated circuit with replacement gate stacks and method of forming same
A first aspect of the invention provides for a method including: forming an interfacial layer in a first opening in a pFET region and a second opening in an...
US-1,007,4573 CMOS nanowire structure
Complimentary metal-oxide-semiconductor nanowire structures are described. For example, a semiconductor structure includes a first semiconductor device. The...
US-1,007,4572 Integrated circuit devices and methods of manufacturing the same
An integrated circuit device includes first and second fin-type active regions having different conductive type channel regions, a first device isolation layer...
US-1,007,4571 Device with decreased pitch contact to active regions
A fin cut process cuts semiconductor fins after forming sacrificial gate structures that overlie portions of the fins. Selected gate structures are removed to...
US-1,007,4570 3D vertical FET with top and bottom gate contacts
A semiconductor device includes a vertical transistor having a gate structure disposed about a channel region thereof. The vertical transistor has a top side...
US-1,007,4569 Minimize middle-of-line contact line shorts
Semiconductor structures and methods of forming such structures are disclosed. In an embodiment, the semiconductor structure comprises a substrate, a dielectric...
US-1,007,4568 Electronic devices and systems, and methods for making and using same
Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing...
US-1,007,4567 Method and system for vertical integration of elemental and compound semiconductors
A method of fabricating a semiconductor structure includes providing an engineered substrate including a polycrystalline substrate, a barrier layer...
US-1,007,4566 Semiconductor device and methods for forming a plurality of semiconductor devices
A method for forming a plurality of semiconductor devices includes forming a plurality of trenches extending from a first lateral surface of a semiconductor...
US-1,007,4565 Method of laser processing for substrate cleaving or dicing through forming "spike-like" shaped damage structures
This invention provides an effective and a method of laser processing for separating semiconductor devices formed on a single substrate (6) or separating high...
US-1,007,4564 Self-aligned middle of the line (MOL) contacts
Disclosed are methods and integrated circuit (IC) structures. The methods enable formation of a gate contact on a gate above (or close thereto) an active region...
US-1,007,4563 Structure and formation method of interconnection structure of semiconductor device
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor...
US-1,007,4562 Self aligned contact structure
Embodiments of present invention provide a method of forming a semiconductor structure. The method includes forming a semiconductor structure having a first...
US-1,007,4561 Backside contact to a final substrate
A device structure is formed using a silicon-on-insulator substrate. The device structure includes a first switch and a second switch that are formed using a...
US-1,007,4560 Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device includes forming an insulating pattern layer on a substrate, conformally forming a first conductive layer with...
US-1,007,4559 Selective poreseal deposition prevention and residue removal using SAM
Methods of discouraging poreseal deposition on metal (e.g. copper) at the bottom of a via during a poresealing process are described. A self-assembled monolayer...
US-1,007,4558 FinFET structure with controlled air gaps
The present disclosure provides a method that includes forming an isolation feature in a semiconductor substrate; forming a first fin and a second fin on the...
US-1,007,4557 Pattern forming method
A first film having a repetitive line pattern is formed on an under film. A second film is formed on a side surface of the first film. The second film has an...
US-1,007,4556 Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device includes the steps of forming a plurality of gate electrodes, forming a first insulating film over the...
US-1,007,4555 Non-contact substrate processing
Embodiments of the present invention provide apparatus and methods for supporting, positioning or rotating a semiconductor substrate during processing. One...
US-1,007,4554 Workpiece loader for a wet processing system
Techniques herein provide a workpiece handling and loading apparatus for loading, unloading, and handling relatively flexible and thin substrates for transport...
US-1,007,4553 Wafer level package integration and method
In a wafer level chip scale package, a wafer level interconnect structure is formed on a dummy substrate with temperatures in excess of 200.degree. C. First...
US-1,007,4552 Method of manufacturing electrostatic chuck having dot structure on surface thereof
A method of manufacturing an electrostatic chuck includes providing a dielectric substrate having a surface which is constituted by a bottom face, and a...
US-1,007,4551 Position detection apparatus, position detection method, information processing program, and storage medium
A hypothesis testing position detection apparatus improves robustness against abnormal detection values, and achieves both high accuracy estimation and...
US-1,007,4550 Plasma stability determination method and plasma processing apparatus
A method and apparatus for determining a stability of plasma in a plasma processing apparatus for performing a plasma processing by converting into plasma a...
US-1,007,4549 Method for acquiring data indicating electrostatic capacitance
In a method for acquiring data indicating an electrostatic capacitance between a focus ring and a measuring device includes a disc-shaped base substrate, sensor...
US-1,007,4548 Chemical liquid discharge mechanism, liquid processing apparatus, chemical liquid discharge method, and storage...
Disclosed is a chemical liquid discharge mechanism. The mechanism includes: a storage portion including a chemical liquid storage space; a diluent supply port...
US-1,007,4547 Photoresist nozzle device and photoresist supply system
Embodiments of a photoresist supply system including a photoresist nozzle device are provided. The photoresist nozzle device includes a tube including a first...
US-1,007,4546 Processing liquid supplying apparatus and processing liquid supplying method
Disclosed is a processing liquid supplying apparatus. The apparatus includes: a processing liquid supply source configured to supply a processing liquid for...
US-1,007,4545 Plasma processing apparatus and plasma processing method
Disclosed is a plasma processing apparatus for performing a processing on a processing target substrate by applying of plasma of a processing gas to the...
US-1,007,4544 Developer free positive tone lithography by thermal direct write
A method for lithographic patterning of thin films. A thin film is deposited on a substrate and the film is exposed to optical energy from a focused laser to...
US-1,007,4543 High dry etch rate materials for semiconductor patterning applications
Methods and apparatuses for depositing low density spacers using atomic layer deposition for negative patterning schemes are provided herein. Methods involve...
US-1,007,4542 Substrate processing method and substrate processing apparatus
There is provided a substrate processing method which includes polishing a rear surface of a substrate before a pattern exposure such that the rear surface is...
US-1,007,4541 Deposition of smooth metal nitride films
In one aspect, methods of forming smooth ternary metal nitride films, such as Ti.sub.xW.sub.yN.sub.z films, are provided. In some embodiments, the films are...
US-1,007,4540 III-V semiconductor diode
A stacked III-V semiconductor diode having a p.sup.+ substrate with a dopant concentration of 5*10.sup.18 to 5*10.sup.20 cm.sup.-3, a layer thickness of 50-500...
US-1,007,4539 Semiconductor device, method for manufacturing semiconductor device, inverter circuit, driving device, vehicle,...
A semiconductor device according to an embodiment includes a SiC layer having a first and a second plane; a first electrode having a first region in the SiC...
US-1,007,4538 Methods for crystallizing a substrate using a plurality of laser pulses and freeze periods
Apparatus and methods of treating a substrate with an amorphous semiconductor layer, or a semiconductor layer having small crystals, to form large crystals in...
US-1,007,4537 Method of forming semiconductor structure having sets of III-V compound layers
A method of forming a semiconductor structure includes depositing a first III-V layer over a substrate. The method includes depositing a first III-V compound...
US-1,007,4536 Lattice-mismatched semiconductor structures and related methods for device fabrication
Lattice-mismatched materials having configurations that trap defects within sidewall-containing structures.
US-1,007,4535 Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium
A method of manufacturing a semiconductor device includes forming a film on a substrate by performing a cycle a predetermined number of times. The cycle...
US-1,007,4534 Ultra-conformal carbon film deposition
Embodiments of the disclosure relate to deposition of a conformal carbon-based material. In one embodiment, the method comprises depositing a sacrificial...
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