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Patent # Description
US-1,007,3820 Systems, methods, and interfaces for pagination and display on an access device
A method executed on an access device includes receiving a markup language file where the markup language file contains a portion of primary text and a portion...
US-1,007,3819 Media table for a digital document
A media table can be created by searching a digital document to identify media content within the digital document in a format associated with a client device...
US-1,007,3818 Data processing method, data processing apparatus and processing apparatus
The present invention is a data processing apparatus including a data input/output device for receiving data, a storage for storing the data received by the...
US-1,007,3817 Optimized matrix multiplication using vector multiplication of interleaved matrix values
The present disclosure relates to optimized matrix multiplication using vector multiplication of interleaved matrix values. Two matrices to be multiplied are...
US-1,007,3816 Native tensor processor, and partitioning of tensor contractions
A native tensor processor calculates tensor contractions using a sum of outer products. In one implementation, the native tensor processor preferably is...
US-1,007,3815 System and method for speeding up general matrix-matrix multiplication on the GPU
A method and system for performing general matrix-matrix multiplication (GEMM) operations on a graphics processor unit (GPU) using Smart kernels. During...
US-1,007,3814 Method for representing and solving algebraic equations with a physical or virtual gear system
A method for representing and solving algebraic equations that allows a user to view and solve algebraic equation with a virtual gear system. The virtual gear...
US-1,007,3813 Generating a mixed integer linear programming matrix from an annotated entity-relationship data model and a...
Programmatically generating a mixed integer linear programming ("MIP") matrix, which can then be solved to provide an optimization, based on an annotated...
US-1,007,3812 Digital discrete-time non-foster circuits and elements
A method to implement circuits and circuit elements having one or more ports may include digitizing, using analog-to-digital converters, continuous-time input...
US-1,007,3811 Systems and methods for monitoring health of vibration damping components
A method for health monitoring of a damper associated with a landing gear is described which includes receiving sensor data from a pressure transducer and an...
US-1,007,3810 Parallel processing device and parallel processing method
A parallel processing device includes processors that execute respective processes and cause an FPGA circuit to process part of the processes. A first processor...
US-1,007,3809 Technologies for scalable remotely accessible memory segments
Technologies for one-side remote memory access communication include multiple computing nodes in communication over a network. A receiver computing node...
US-1,007,3808 Multichip package link
Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the...
US-1,007,3807 Logic-based decoder for crosstalk-harnessed signaling
A logic-based decoder recovers binary data from ternary Crosstalk-Harnessed Signaling (CHS) streams with lower part cost, complexity and power consumption than...
US-1,007,3806 Apparatus and methods for providing a reconfigurable bidirectional front-end interface
An apparatus and methods are disclosed for a bidirectional front-end circuit included within a system on chip (SoC). The bidirectional front-end circuit...
US-1,007,3805 Virtual expansion ROM in a PCIe environment
Methods and structure for utilizing a virtual Expansion ROM. One exemplary embodiment is a management device. The management device includes a memory, a...
US-1,007,3804 Computer, server, module, connector set, assembly method, control method, and opening control program
A computer includes: first and second connectors; and a data transmission path. The first connector includes: a first connector body to which at least a first...
US-1,007,3803 Apparatus and methods for dynamic role switching among USB hosts and devices
Apparatus and methods for USB hosts and USB devices to dynamically switch roles such that a product which initially operates as a USB host may instead operate...
US-1,007,3802 Inter-cluster data communication network for a dynamic shared communication platform
The disclosure relates to a data communication network connecting a plurality of computation clusters. The data communication network is arranged for receiving...
US-1,007,3801 Computer and method of controlling I/O switch of computer
A computer achieves an increase in throughput by controlling a connection state between each port of an I/O controller and an I/O switch, thereby improving...
US-1,007,3800 Coupling controller, information processing apparatus and coupling control method
A coupling controller that performs coupling control of a device with a bus includes a decision circuit configured to decide whether a voltage level of a signal...
US-1,007,3799 Programmable data width converter device, system and method thereof
The present disclosure pertains to a programmable data width converter device, system and method thereof. Programmable data width converter (pDWC) of the...
US-1,007,3798 Hardware control interface for IEEE standard 802.11
A standardized 802.11 hardware control interface may be provided such that a driver may communicate with any one or more of a variety of network adapters.
US-1,007,3797 Data processor device supporting selectable exceptions and method thereof
A processor begins exception processing in response to an exception event. Exception processing by the processor is halted during exception processing to...
US-1,007,3796 Sending packets using optimized PIO write sequences without SFENCES
Method and apparatus for sending packets using optimized PIO write sequences without sfences. Sequences of Programmed Input/Output (PIO) write instructions to...
US-1,007,3795 Data compression engine for I/O processing subsystem
In a system and method for emulating a circuit design, an emulation system receives input instructions from a host device executing the emulation and returns...
US-1,007,3794 Mobile application builder program and its functionality for application development, providing the user an...
A mobile "Applications Builder" established on the user's mobile handheld device creates a bucket or container for mobile applications (Apps) and selectively...
US-1,007,3793 Data processor
A data processor includes an access target with the address assigned to a memory space, an access subject that gains access to the access target while...
US-1,007,3792 Device, system, and method for detecting, identifying, and communicating with a storage medium
A device includes: a storage medium control unit provided for each type of storage medium to at least read out information from the storage medium; a linkage...
US-1,007,3791 Securing files
Data security access and management may require a server dedicated to monitoring document access requests and enforcing rules and policies to limit access to...
US-1,007,3790 Electronic system with memory management mechanism and method of operation thereof
An electronic system includes: a processor configured to access operation data; a high speed local memory, coupled to the processor, configured to store a...
US-1,007,3789 Method for load instruction speculation past older store instructions
A system includes a memory, a cache including multiple cache lines; and a processor. The processor may be configured to retrieve, from a first cache line, a...
US-1,007,3788 Information processing device and method executed by an information processing device
An information processing device includes a first memory and a processor configured to receive first data from the second memory, receive second data from the...
US-1,007,3787 Dynamic powering of cache memory by ways within multiple set groups based on utilization trends
A set associative cache memory comprises an M.times.N memory array of storage entries arranged as M sets by N ways, both M and N are integers greater than one....
US-1,007,3786 Apparatuses and methods for compute enabled cache
The present application includes apparatuses and methods for compute enabled cache. An example apparatus includes a compute component, a memory and a controller...
US-1,007,3785 Up/down prefetcher
In a processing system comprising a cache, a method includes monitoring demand cache accesses for a thread to maintain a first running count of a number of...
US-1,007,3784 Memory performance when speculation control is enabled, and instruction therefor
Throttling execution in a transaction operating in a processor configured to execute memory instructions out-of-program-order in a pipelined processor, wherein...
US-1,007,3783 Dual mode local data store
A system and method for efficiently processing access requests for a shared resource are described. Each of many requestors are assigned to a partition of a...
US-1,007,3782 Memory unit for data memory references of multi-threaded processor with interleaved inter-thread pipeline in...
A memory unit for handling data memory references of a multi-threaded processor with interleaved inter-thread pipeline in emulated shared memory architectures,...
US-1,007,3781 Systems and methods for invalidating directory of non-home locations ways
Systems and methods for invalidating a way of a directory for non-home locations (DNHL) set that stores an identifier of a home location of an address is...
US-1,007,3780 Methods and systems for tracking addresses stored in non-home cache locations
Systems and methods for tracking addresses stored in non-home locations in a cache. A method includes determining if an address that is to be stored in a cache...
US-1,007,3779 Processors having virtually clustered cores and cache slices
A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is...
US-1,007,3778 Caching in multicore and multiprocessor architectures
A multicore processor comprises a plurality of cache memories, and a plurality of processor cores, each associated with one of the cache memories. Each of at...
US-1,007,3776 Shadow tag memory to monitor state of cachelines at different cache level
A processing system includes a plurality of processor cores and a plurality of private caches. Each private cache is associated with a corresponding processor...
US-1,007,3775 Apparatus and method for triggered prefetching to improve I/O and producer-consumer workload efficiency
An apparatus and method are described for a triggered prefetch operation. For example, one embodiment of a processor comprises: a first core comprising a first...
US-1,007,3774 Managing input/output operations for shingled magnetic recording in a storage system
A system and method for improving the management of data input and output (I/O) operations for Shingled Magnetic Recording (SMR) devices in a network storage...
US-1,007,3773 Instruction paging in reconfigurable fabric
Circular buffers containing instructions that enable the execution of operations on logical elements are described where data in the circular buffers is swapped...
US-1,007,3772 Copy-on-write in cache for ensuring data integrity in case of storage system failure
Various embodiments for managing data integrity in a computing storage environment, by a processor device, are provided. In one embodiment, a method comprises...
US-1,007,3771 Data storage method and system thereof
A data storage method and a system thereof are disclosed. The data storage method includes allocating a first logical block and a second logical block, which...
US-1,007,3770 Scheme for determining data object usage in a memory region
Method and apparatus for managing memory is disclosed herein. In one embodiment, the method includes specifying a first load-monitored region within a memory,...
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