BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates in general to sense amplifiers for semiconductor read-only memories (ROMs). In particular, the present invention relates to a multi-stage sense amplifier for ROM devices capable of storing more than one bit of datain one single memory cell unit.

2. Technical Background

ROM's are widely used semiconductor integrated circuit (IC) memory storage devices for digital electronic equipment, and, in particular, microprocessor-based computer systems. Conventional digital circuitry in ROM's employ sense amplifiers tosense the content of an addressed memory cell in order to "read" a memory location.

State-of-the-art semiconductor ROM IC devices, however, store a single binary bit of information in each of their memory cell units. That is to say, the sensed result with respect to each memory cell unit of the ROM device is identified betweentwo electrical potential stages. In other words, the memory content of a ROM memory cell as read is either a logical 1 or a logical 0.

Enlargement of the memory storage capacity (by increasing the number of memory cells), as well as reducing the physical size of the semiconductor device, have been targets which the semiconductor memory industry has been pursuing. Enlargedmemory capacity and reduced memory semiconductor die size represent increased functionality and reduced cost, both of which are positive factors in the merchandising of semiconductor memory products. The greatest effort in the art has been concernedwith the reduction of the device dimensions in order to squeeze more memory cell units in the same semiconductor die area. This approach, however, is limited by the current state of the art in resolving details during semiconductor processing.

SUMMARY OF THE INVENTION

The present invention allows for a reduction in size of ROM device by allowing more than one bit of information to be stored in a given memory cell. A multi-stage sense amplifier is disclosed for use with read-only memory having a memory arrayconsisting of a large number of memory cell units. The sense amplifier senses currents flowing through a transistor in the memory cell units of the read-only memory. The memory cell unit transistors are programmed with one of four current capacitycharacteristics. The sense amplifier also comprises three current comparators coupled to the sense amplifier, with each of the comparators having a current comparing unit for comparing the sensed current flowing through the memory cell unit transistorsto the current flowing through the comparators. An output of each of the three comparators is provided for identifying whether or not the current of a four capacity characteristics flowing through the memory cell unit transistors is larger than thecurrent flowing through the comparator. Each of the outputs of the comparators is combined to represent the data stored in each of the memory cell units of the read-only memory having two bits per memory cell unit.

BRIEF DESCRIPTION OF THEDRAWING

Other objects,, features and advantages of the present invention will become apparent by way of the following detailed description of the preferred but non-limiting embodiment. The description is made with reference to the accompanied drawings,wherein:

FIG. 1 schematically shows the top view of the layout of a single memory cell unit in the semiconductor integrated circuit device in accordance with a preferred embodiment of the present invention.

FIG. 2 is a schematic diagram showing a multi-stage sense amplifier in accordance with a preferred embodiment of the present invention;

FIG. 3 shows the output characteristics of the multistage sense amplifier of FIG. 2 sensing memory cell units with different storage contents characteristics; and

FIG. 4 shows a truth table of decoder electronic circuitry for the memory device in accordance with the preferred embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

The basic underlying concept of the present invention is outlined in FIG. 1, which schematically depicts a top view of the layout of a single memory cell unit in a semiconductor integrated circuit device according to a preferred embodiment of thepresent invention. In this figure, a polysilicon word line WL in the memory array in the ROM IC device overlies both source S and drain D regions of the memory device. A channel region 60 of the memory cell unit is formed underneath the coverage of theword line WL between source S and drain D regions.

In a conventional semiconductor ROM IC device, channel region 60 is selectively implanted with ions depending on whether the memory cell unit contains a logical zero or a logical one.

In accordance with the present invention, channel region 60 for each memory cell unit in the memory array of the ROM device is divided into three generally equal-width portions, as is identified in the FIG. 1 by the two broken lines depicted inchannel region 60. During that phase of ROM device manufacturing when digital information is programmed into the ROM device, the entire channel region 60 of each memory cell unit can be subjected to an ion implantation procedure which results in fourpossible outcomes:

(1) No ions are implanted in any portion of channel region 60. When turned on, the current which flows is equal to I.sub.1.

(2) One-third of the width of the channel region 60 is subjected to ion implantation. When turned on, the current which flows is equal to I.sub.2.

(3) Two-thirds of the width of the channel region 60 is subjected to ion implantation. When turned on, the current which flows is equal to I.sub.3.

(4) The entire width of the channel region is subjected to ion implantation. When turned on, the current which flows is equal to I.sub.4.

With this arrangement, each cell of the ROM device has four possible states which can be detected by a multi-stage sense amplifier which will be described later. During reading operations the sensed voltage on the word line WL will exhibit oneof four possible voltage values depending on whether zero, one, two or three portions of the entire channel region width were exposed during programming by the ion implantation procedure. With the help of suitable decoder circuitry, the four voltagevalues can each be identified as one of four digital values, for example, 00, 01, 10 and 11 when expressed in two-bit binary format. Thus the output of the retrieved information from a single memory cell comprises two bits of stored information or data.

Thus, as described above, the basic underlying principle of the present invention is to employ one memory cell to store two bits of information, rather than one bit of information as done in prior art ROM IC devices. This results in a two-foldmemory capacity increase for the exemplified ROM IC device when the memory cell unit dimension remain equal.

FIG. 2 is a schematic diagram of the multi-stage sense amplifier, mentioned above, in accordance with a preferred embodiment of the present invention. As can be observed in this figure, the multi-stage sense amplifier comprises a sense amplifier10 and three comparators 20, 30 and 40. A description of each of these primary constituent parts follows. Notice should be taken that the memory cell unit of the memory array selected to be read is symbolized in the schematic diagram of FIG. 2 as amemory cell unit transistor C.sub.1. As is familiar to persons skilled in this art, each memory cell unit is represented by a transistor device in a schematic diagram. The circuitry for selecting a particular transistor to be read is well known in theart and therefore is not described in detail herein.

First, reference is made to sense amplifier 10. As is seen in FIG. 2, the sense amplifier 10 is utilized for the sensing the electrical potential across the memory cell unit C.sub.1 when read. Sense amplifier 10 includes two PMOS transistorsQP.sub.1 and QP.sub.2, two NMOS transistors QN.sub.1 and QN.sub.2, an NMOS block transistor BN.sub.1, an NMOS select transistor SN.sub.1, and a NOR gate NOR.sub.1.

The gate of PMOS transistor QP.sub.1 is tied to ground, its source is tied to the system power source voltage V.sub.cc, and its drain connected to the drain of NMOS transistor QN.sub.2. PMOS transistor QP.sub.2 has its source tied to V.sub.cc,and its drain and gate are tied together and are connected to the drain of NMOS transistor QN.sub.2. Gates of NMOS transistors QN.sub.1 and QN.sub.2 are both strobed by a sense enable signal SEN of the ROM device indirectly through NOR gate NOR.sub.1.

The sense enable signal SEN is utilized to preserve device power consumption of the entire ROM IC device when it is not being accessed. The sources of NMOS transistors QN.sub.2 and QN.sub.2 are tied together and connected to the drain of NMOSblock transistor BN.sub.1. The source of NMOS block transistor BN.sub.1 is connected to the drain of NMOS select transistor SN.sub.1, which, in turn has its source connected to the drain of memory cell unit transistor C.sub.1. Transistor C.sub.1, onthe other hand has its source tied to ground. The gate of the NMOS block transistor BN.sub.1 is strobed by a block signal BKN, and the gate of NMOS select transistor SN.sub.1 is strobed by a select signal SEL. With the application of the block signalBKN that drives NMOS block transistor BN.sub.1, the memory electronics can be divided into sections that are convenient for the conservation of power consumption.

Next, referring to comparators 20, 30 and 40, they share a similar circuitry configuration which is similar to that of the sense amplifier 10, as can be seen in FIG. 2. The only difference is that the comparators 20, 30 and 40 each has a currentcomparing unit 22, 32 and 42 respectively in place of the memory cell unit transistor C.sub.1 in the sense amplifier 10.

Other than two above, the comparators 20, 30 and 40 each comprise two PMOS transistors QP.sub.11 and QP.sub.12, two NMOS transistors QN.sub.11 and QN.sub.22, an NMOS block transistor BN.sub.11, an NMOS select transistor SN.sub.11, a NOR gateNOR.sub.11, and the current comparing units 22, 32 and 42 respectively. It should be pointed out that the same reference characters, but with differing subscripts, are used in the three independent comparators for the purpose of simplicity ofdescription of the present invention. The use of the same characters for these various transistors suggests that they are not only comparably identical transistors, but that their structural dimensions are also the same. In other words, the dimensionof PMOS transistors QP.sub.11 and QP.sub.12 are the same as that of QP.sub.1 and QP.sub.2 respectively. Likewise, in terms of structural dimensions, transistors QN.sub.11 and QN.sub.12 are the same as that of QN.sub.1 and QN.sub.2 respectively, whileBN.sub.11 is the same as BN.sub.1, and SN.sub.11 is the same as SN.sub.1.

The three comparators 20, 30 and 40 each has a current comparing unit 22, 32 and 42 respectively. Each current comparing unit has a similar structural configuration of two pairs of two serially connected NMOS transistors connected in parallel,as shown in the figure. Each pair of NMOS transistors connected in series have the same physical dimensions, but each pair is different in dimension compared to the other pair of transistors connected in parallel therewith. For example, in currentcomparing unit 22, NMOS transistors CT.sub.11 and CT.sub.12 have the same physical dimensions, and CT.sub.21 and CT.sub.22 have the same physical dimensions, but the latter pair have different dimensions compared to that: of the first-mentioned pair. NMOS transistors CT.sub.21 and CT.sub.22 also appear in comparator 30. That means that those transistors in comparator 30 have the same size as the similarly identified transistors in comparator 20.

There is a similar arrangement in current comparing units 32 and 42 with respect to NMOS transistors CT.sub.31, CT.sub.32. Thus, a total of four different sizes of series-connected transistor pairs CT.sub.11,CT.sub.12 ; CT.sub.21,CT.sub.22 ;CT.sub.31,CT.sub.32 and CT.sub.41,CT.sub.42 are employed in the three current comparing units 22, 32 and 42. Thus current comparing units 22 and 32 have similar transistor pairs CT.sub.21 /CT.sub.22 in one of their two parallel shunt branches, and, onthe other hand, the current comparing units 32 and 42 have the similar transistor pairs CT.sub.31 /CT.sub.32 in one of their two parallel shunt branches.

This arrangement of the NMOS transistor physical dimensions provides four transistor types which correspond respectively to the four possible levels of ion implantation in the channel regions of the memory cell unit transistors in the memoryarray of the ROM device, as described above with reference to FIG. 1.

All the twelve NMOS transistors in the three current comparing units are gated or strobed by a common word line signal W.sub.N. The currents flow through the NMOS transistors. CT.sub.11, CT.sub.21, CT.sub.31 and CT.sub.41, when the currentcomparing units are gated on, are I.sub.1, I.sub.2, I.sub.3 and I.sub.4, respectively. As previously mentioned, the currents flowing through each of the memory cell unit transistors C.sub.1 of the ROM device, which have the four possible levels of ionimplantation, are also either I.sub.1, I.sub.2, I.sub.3 or I.sub.4 (respectively corresponding to zero, one, two or three of the one-third width channel regions being exposed to ion implantation during device programming phase). Then, the currentflowing through the current comparing units 22, 32 and 42 will be 1/2(I.sub.1 +I.sub.2), 1/2(I.sub.2 +I.sub.3) and 1/2(I.sub.3 +I.sub.4) respectively.

Referring again to FIG. 2, three output ports OP.sub.0, OP.sub.1 and OP.sub.2 are tapped at the drains of the PMOS transistors QP.sub.12 of the current comparing units 20, 30 and 40 respectively. The signal on any of output ports OP.sub.0,OP.sub.1 and OP.sub.2 will be a high level, i.e. a logical 1, whenever the corresponding current flowing through the corresponding current comparing unit 20, 30 or 40 is exceeded by the current flowing through the memory cell unit transistor C.sub.1 thenconnected to the current sense amplifier 10. Otherwise, the signal on an output port will be low, or logical 0.

FIG. 3 of the drawing shows the output characteristics of the multi-stage sense amplifier of FIG. 2 sensing memory cell units with different storage contents characteristics. The abscissa of the axis of the plot represents the output portsOP.sub.0, OP.sub.1 and OP.sub.2 generally designated as OP.sub.210 in the drawing. The ordinates of the axis, on the other hand, represents the current.

It should be pointed out that the currents I.sub.1, I.sub.2, I.sub.3 and I.sub.4 are arranged so as to satisfy the condition that I.sub.1 <I.sub.2 <I.sub.3 <I.sub.4, as is reflected in FIG. 3. To satisfy this condition, the physicaldimensions of the transistors, as well as the channel region width are adjusted accordingly, as persons skilled in this art can appreciate.

Assume, for example, the current flowing through the memory cell unit transistor C.sub.1 is I.sub.1, with its channel region having no portion thereof programmed by ion implantation. This implies a physical dimension of the memory cell unittransistor C.sub.1 virtually equal to that of the transistors CT.sub.11 and CT.sub.12 in current comparing unit 20. As is seen in FIG. 3, the current I.sub.1 is the smallest in the shown scales, which indicates the fact that it is smaller than thecurrents flowing in any of the current comparing units 20, 30 and 40. Therefore, the output voltages, or their equivalent logical levels, as measured at output ports OP.sub.0, OP.sub.1 and OP.sub.2 (generally designated as OP.sub.210 in FIG. 3), will be0, 0 and 0, as represented on the abscissa by the 000.

As another example, assume the current flowing in the memory cell unit transistor C.sub.1, is I.sub.3, which occurs when two-thirds of the channel width of transistor C.sub.1 was programmed by ion implantation, then the logical levels as measuredat output ports OP.sub.0, OP.sub.1 and OP.sub.2 will be 0, 1 and 1, as represented in the abscissa by a 011.

At the output ports OP.sub.0, OP.sub.1 and OP.sub.2 of the sense amplifier as shown in FIG. 2, a suitable decoder 50 can be readily provided to decode the three-bit sensed logical values into two-bit data for output as the memory cell unittransistors C.sub.1 are being read. FIG. 4 of the drawing sets forth a truth table for such a decoder. The implementation of the decoder is straight forward. In FIG. 4, the logical values of the output ports OP.sub.0, OP.sub.1 and OP.sub.2 areconverted into two data bits O.sub.1 and O.sub.0, with the decoding expression listed therein. Persons skilled in this art can appreciate the fact that other similar electronic logics means can be employed as well to serve the decoding requirementsequally well.

Thus, in accordance with the disclosure of the present invention, a single memory cell unit in a memory array of a ROM IC device can be utilized to store two bits of data, rather than only one bit as is done in the prior art. A programmingscheme has been disclosed in relation to channel region width management for the memory cell unit transistors, as well as for transistors in the multi-stage sense amplifier. These features facilitate better utilization of a single memory cell. Itshould, however, be pointed out that the above described embodiments of the memory cell unit and multi-stage sense amplifier, as well as the decoding means, are only for the purpose of the description clarity of the present invention and not for limitingthe scope of the invention. Having disclosed the invention in connection with a preferred embodiment thereof, modification will now suggest itself to those skilled in the art. For example, with suitable adjustment in the memory cell unit channel regionwidth, as well as the provision of the matching sense amplifier and decoder means, the single memory cell can be arranged to store more than two bits of data (for example three or more bits of data), as persons in the art will appreciate after readingthe above description of the present invention.

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