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Searching: computer memory





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Patent # Description
US-9,953,216 Systems and methods for performing actions in response to user gestures in captured images
Systems, methods, and computer-readable media are provided for performing actions in response to gestures made by a user in captured images. In accordance with...
US-9,953,211 Image recognition apparatus, image recognition method and computer-readable medium
An image recognition apparatus, method and non-transitory computer-readable storage medium are disclosed. An image recognition apparatus may include a memory...
US-9,953,193 Operating systems for an RFID tag
In embodiments of the present invention improved capabilities are described for a wireless computing device, comprising an antenna; an analog block for...
US-9,953,125 Design/technology co-optimization platform for high-mobility channels CMOS technology
Embodiments of the present invention may provide the capability to design SRAM cells may be designed that is compatible with the requirements of InGaAs...
US-9,953,044 Radix sort acceleration using custom ASIC
An information processing system, computer readable storage medium, and method for accelerated radix sort processing of data elements in an array in memory. The...
US-9,953,027 System and method for automatic, unsupervised paraphrase generation using a novel framework that learns...
A system includes a question answering system executed by a computer, a processor, and a memory coupled to the processor. The memory is encoded with...
US-9,952,979 Methods and systems for direct memory access operations
Systems and methods for a direct memory access (DMA) operation are provided. The method includes receiving a host memory address by a device coupled to a...
US-9,952,976 Allowing non-cacheable loads within a transaction
A computer allows non-cacheable loads or stores in a hardware transactional memory environment. Transactional loads or stores, by a processor, are monitored in...
US-9,952,975 Memory network to route memory traffic and I/O traffic
According to an example, memory traffic including memory access commands is routed between compute nodes and memory nodes in a memory network. Other traffic is...
US-9,952,972 Iterator register for structured memory
Loading data from a computer memory system is disclosed. A memory system is provided, wherein some or all data stored in the memory system is organized as one...
US-9,952,971 Distributed cache arrangement
Systems and methods that aggregate memory capacity of multiple computers into a single unified cache, via a layering arrangement. Such layering arrangement is...
US-9,952,951 Preserving coredump data during switchover operation
One or more techniques and/or computing devices are provided for preserving coredump data. A first storage controller, of a first storage cluster, may have a...
US-9,952,941 Elastic virtual multipath resource access using sequestered partitions
Technologies for virtual multipath access include a computing device configured to sequester a recovery partition from a host partition while allowing the...
US-9,952,930 Reallocation in a dispersed storage network (DSN)
A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational...
US-9,952,905 Methods and systems to identify and migrate threads among system nodes based on system performance metrics
Methods and systems to identify computer system nodes to which a computer program thread is to be migrated. An example method disclosed herein includes storing...
US-9,952,890 Kernel state data collection in a protected kernel environment
Methods, systems, and computer program products are included for collecting kernel data in a protected kernel environment. A method includes allocating a first...
US-9,952,879 Application pre-layout in byte-addressable persistent random access memory
A software layout system is described herein that speeds up computer system boot time and/or application initialization time by moving constant data and...
US-9,952,860 Dynamic memory management for a virtual supercomputer
Present invention embodiments enable the handling of various index-memory architectures for a virtual supercomputer that would allow for a heterogeneous storage...
US-9,952,805 Storage system and data write method using a logical volume to either store data successfully onto a first...
A processor receives a command from a server computer to designate a plurality of addresses related to a plurality of logical storage areas, and write a...
US-9,952,804 Hardware transaction transient conflict resolution
In an approach for resolving terminated transactions in a transactional memory environment, a processor initiates a hardware transaction in a computing...
US-9,952,802 Volatile memory erasure by controlling refreshment of stored data
A method of erasing volatile memory requiring refreshment using refresh circuitry to maintain data storage, the method comprising controlling the refresh...
US-9,952,798 Repartitioning data in a distributed computing system
Methods, systems, and apparatus for allocating, by a source of one or more sources, a segment of a data file of a transient memory for exclusive access by the...
US-9,952,785 Enabling non-volatile random access to data
Embodiments of the present disclosure relate to a method, computer program product and a system for enabling non-volatile random access to data where in...
US-9,952,774 Hierarchical pre-fetch pipelining in a hybrid memory server
A method, hybrid server system, and computer program product, prefetch data. A set of prefetch requests associated with one or more given datasets residing on...
US-9,951,459 Systems and methods for monitoring sanitation agents in a laundry system
A system for monitoring sanitation agents in a laundry machine comprises a plurality of channels. Each channel has an input port, an output port, and a glass...
US-9,950,263 Method for mobile gaming systems
A mobile gaming device may execute computer code and/or software from a non-transitory computer readable memory. A user may input commands via a plurality of...
US-9,950,248 Electronic puzzles
A computing system of an electronic puzzle includes a memory, an electronically controlled lock, and a plurality of sensors to generate sensor data. The...
US-9,950,183 Impedance spectroscopy for defibrillator applications
A computing device includes a memory configured to store instructions. The computing device also includes a processor to execute the instructions to perform...
US-9,949,658 Computer-aided localization of site of origin of cardiac activation with discriminator leads
A method for quantifying, during pacemapping, a comparison of a BSPM of interest to a pace site BSPM. The method may include receiving at a computing device a...
US-9,949,351 Method for controlling mobile terminal and program for controlling mobile terminal
A method for controlling a mobile terminal that controls lighting devices that illuminate spaces, the terminal including a display and a memory. The method...
US-9,949,251 Methods and user equipments for data demodulation
Methods and user equipment (UE) for data demodulation. A UE comprises a receiver (Rx), a transmitter (Tx), a demodulator, a decoder, a processor, and a memory....
US-9,949,237 Method and apparatus for facilitating machine gateway operation
An apparatus (20) for providing facilitation of mobile gateway operation may include at least one processor and at least one memory including computer program...
US-9,949,186 Resource block identifications (RBIDs) for neighbor station resource requests
Computer readable media, methods, and apparatus for resource block identification (RBIDs) for neighbor station resource requests are disclosed. An apparatus of...
US-9,949,162 Reporting for MBMS
The invention relates to an apparatus including at least one processor and at least one memory including a computer program code, the at least one memory and...
US-9,948,958 Low complex deblocking filter decisions
The present disclosure relates to deblocking filtering, which may be advantageously applied for block-wise encoding and decoding of images or video signals. In...
US-9,948,934 Estimating rate costs in video encoding operations using entropy encoding statistics
A component of an entropy encoding stage of a block processing pipeline (e.g., a CABAC encoder) may, for a block of pixels in a video frame, accumulate counts...
US-9,948,910 Method of and apparatus for simultaneously displaying video input along with supplementary information
One aspect of the invention includes an apparatus that simultaneously displays the video input and supplementary information, having a video overlay device, and...
US-9,948,821 Non-transitory computer-readable recording medium storing computer-readable instructions for causing...
An information processing device may accept an input of a first print instruction. The information processing device may send first print data to a printer in...
US-9,948,761 Non-transitory computer-readable medium and portable device
A non-transitory computer-readable medium having a computer program readable by a computer of a portable device connectable to an image input device and image...
US-9,948,750 Tailoring content to be delivered to mobile device based upon features of mobile device
A method, system and computer program product for delivering tailored specific content to a mobile device. A shim application is provided to the mobile device...
US-9,948,714 Assigning a data item to a storage location in a computing environment
The computer detects a request from a first computer to store a data item, and determines if a volatile memory in a second computer comports with an isolation...
US-9,948,704 Determining a best fit coordinator node in a database as a service infrastructure
A computer-implemented method for determining a coordinator node in a database as a service (DBaaS) infrastructure includes receiving, via a processor on a...
US-9,948,660 Computer security based on hierarchical cache latency signature authentication
A processor is coupled to a hierarchical memory structure which includes a plurality of levels of cache memories that hierarchically cache data that is read by...
US-9,948,545 Apparatus and method for failover of device interconnect using remote memory access with segmented queue
A first remote memory access link is established between a first communications interface card on the first computing device and a second communications...
US-9,948,471 Tamper-resistant non-volatile memory device and integrated circuit card
A non-volatile memory device according to an aspect of the present disclosure includes a memory array that includes non-volatile memory cells; a read circuit...
US-9,948,466 Devices, systems, and methods for authenticated intravascular device use and reuse
Devices, systems, and methods for reconditioning an intravascular device for reuse are provided. The method includes reading first security data from a memory...
US-9,948,463 Multivariate public key signature/verification system and signature/verification method
Multivariate public key signature/verification system including a signature module and a verification module. The signature module contains a processor, first...
US-9,948,306 Configurable gate array based on three-dimensional printed memory
The present invention discloses a configurable gate array based on three-dimensional printed memory (3D-P). It comprises an array of configurable computing...
US-9,948,100 Zero droop voltage control for smart inverters
Systems and methods for controlling grid voltage include a distribution power network and one or more smart inverters at or near the edge of the distribution...
US-9,947,386 Thermal aware data placement and compute dispatch in a memory system
A method of managing thermal levels in a memory system may include determining an expected thermal level associated with each of a plurality of locations in a...
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