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Searching: cpu processor
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| Patent # | Description |
|---|---|
| US-7,822,899 |
Data processor and control system Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller... |
| US-7,818,746 |
System and method for benchmarking using a multi-threaded load generator According to one embodiment, a benchmarking system comprises a processor and a multi-threaded load generator. The multi-threaded load generator uses events for... |
| US-7,818,485 |
IO processor An IO processor includes an embedded central processing unit (CPU), a switch connected to the embedded CPU, an external CPU bus controller connected to the... |
| US-7,814,366 |
On-demand CPU licensing activation A method and apparatus for on-demand CPU licensing. An embodiment of a processor license system includes an agent to determine that a computer processing element... |
| US-7,814,252 |
Asymmetric multiprocessor An asymmetric multiprocessor capable of increasing a degree of freedom of distributed processing, minimizing a processing load on each processor (CPU), and... |
| US-7,814,223 |
Packet communication device, packet communication system, packet
communication system, packet communication... A transmit packet generated by a CPU 1 is held in a buffer 100a (100b). From among packets received from Ethernet 820a (820b), a packet, a destination of which... |
| US-7,809,847 |
Network interface device that can transfer control of a TCP connection to
a host CPU An intelligent network interface card (INIC) or communication processing device (CPD) works with a host computer for data communication. The device provides a... |
| US-7,809,547 |
Host computer system emulating target system legacy software and providing
for incorporating more powerful... As manufacturers of very fast and powerful commodity processors continue to improve the capabilities of their products, it has become practical to emulate the... |
| US-7,802,256 |
Class scheduler for increasing the probability of processor access by
time-sensitive processes A method and apparatus for enabling a general purpose operating system to maximize the probability of time-sensitive threads, e.g., multimedia threads, gaining... |
| US-RE41,716 |
Modular signature and data-capture system and point of transaction payment
and reward system A modular signature and data capture device employs a standardized ISA bus, standardized communication ports, and standardized .times.86 CPU architecture to... |
| US-7,796,583 |
Packet handler for high-speed data networks An improved packet handler for VoIP cable modems and other high-speed digital devices includes a direct communication link via hardware among internal processing... |
| US-7,787,629 |
Use of graphics processors as parallel math co-processors for password
recovery In a computer system having a central processing unit (CPU) and a graphics processing unit (GPU), a system, method and computer program product for recovering a... |
| US-7,783,880 |
Method and apparatus for secure internet protocol (IPSEC) offloading with
integrated host protocol stack management The invention provides mechanisms for transferring processor control of secure Internet Protocol (IPSec) security association (SA) functions between a host and a... |
| US-7,774,584 |
Discrete multi-tone (DMT) system and method that communicates a data pump
data stream between a general purpose... The apparatus and method herein splits the function of a digital subscriber line (DSL) modem data pump between a digital signal processor (DSP 106) and a general... |
| US-7,769,088 |
Context adaptive binary arithmetic code decoding engine A CABAC decoding engine is devised to cover all aspects of decoding all CABAC-coded syntax elements for AVC. This CABAC decoding engine acts like a Co-processor... |
| US-7,761,877 |
L driving method for driving program/instruction execution, and
architecture and processor thereof The invention relates to computer architecture technology in the computer field. More specifically, the invention relates to a novel driving method for driving... |
| US-7,761,876 |
Method and system for balancing the load on media processors based upon
CPU utilization information The present invention is a method and system for balancing the load on processors based upon the CPU utilization information of the processors. Real time CPU... |
| US-7,761,756 |
Circuit configuration with serial test interface or serial test
operating-mode procedure The invention relates to a circuit configuration with a serial test interface (TIF) to control a test operation mode, a freely programmable digital processor... |
| US-7,761,689 |
Programming a digital processor with a single connection A digital processor is coupled to a processor programmer through a single programming connection (e.g., terminal, pin, etc.) coupled to the single conductor... |
| US-7,761,122 |
System for improving overall battery life of a GSM communication device Disclosed is a system for improving the overall battery life of a GSM device according to an optimization mechanism for suspending neighbor-cell scanning in a... |
| US-7,757,107 |
Maintaining a power budget A server is capable of maintaining a power budget. The server comprises a central processing unit (CPU), a management processor, a power measurement circuit, and... |
| US-7,756,489 |
Software defined radio and library configuration therefor A radio communication apparatus having a radio modem for processing a signal in a radio frequency band, a signal processor for processing a base band of a... |
| US-7,752,372 |
PCI express (PCIe) communication system A device, system and method adapted to expand a high speed data bus, such as a PCI Express (PCIe) bus, over a serial link with an expansion unit having a high... |
| US-7,751,310 |
Fault tolerant duplex computer system and its control method There is disclosed a fault tolerant duplex computer system capable of increasing accuracy of processing to be continued by collecting trouble information without... |
| US-7,751,142 |
Portable device with freefall detection or audio processing subsystem and
freefall detection or audio... In a class of embodiments, a method and apparatus for detecting freefall of a disk device (thereby predicting that the disk device will likely suffer imminent... |
| US-7,750,954 |
Camera control device A camera control circuit stores an image picked up by a CCD into an internal memory. A CPU of a main processor circuit gives an instruction of reading out image... |
| US-7,742,273 |
Self-protected, intelligent, power control module An intelligent, self-protected control module which is a fully protected and configured as a multi-terminal device controlling a number of power field-effect... |
| US-7,739,532 |
Method, apparatus and system for enhanced CPU frequency governers A method, apparatus and system enable enhanced processor frequency governors to comprehend virtualized platforms and utilize predictive information to enhance... |
| US-7,739,434 |
Performing a configuration virtual topology change and instruction
therefore In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest... |
| US-7,734,860 |
Signal processor For every sampling period of a DSP 100, a timing generator 200 requests a CPU 300 to release a bus and provides a DSP 100 access time period to make an external... |
| US-7,734,852 |
Modular computer system A modular computer system (20) including a universal connectivity station (UCS) (22) interconnected to a plurality of remote modules (30, 32, 34, 36, 38, 42) via... |
| US-7,732,699 |
Central processing unit for singing room machinery and MP3 A central processing unit (CPU) for an MP3 player and a karaoke system makes it possible to reduce the size of the MP3 and the karaoke system by integrally... |
| US-7,730,330 |
System and method for saving and restoring a processor state without
executing any instructions from a first... A CPU (1) automatically preserves the CPU context in a computer memory (5) that remains powered-up when the CPU is powered down in sleep mode. By means of the... |
| US-7,728,887 |
Image processing device and method Image data of a digital signal is inputted to a digital signal processor. A CPU reads out color correction coefficients from a ROM. Weights are added to the... |
| US-7,725,694 |
Processor, microcomputer and method for controlling program of
microcomputer A microcomputer includes a CPU capable of performing a plurality of tasks in a parallel time-sharing operation. The tasks include at least one special task... |
| US-7,724,078 |
Adjusting PLL/analog supply to track CPU core supply through a voltage
regulator A processing device includes a Phase Locked Loop (PLL) system with an adjustable power supply designed to track the power supply provided to one or more of the... |
| US-7,715,415 |
Router having a single CPU MAC A network device for transferring data from a first network to a second network comprises a switch comprising a first port adapted to receive a frame of the data... |
| US-7,711,966 |
Dynamic clock frequency adjustment based on processor load In general, the disclosure is directed to techniques for reducing power consumption within computing devices, such as wireless communication devices. A device... |
| US-7,707,296 |
Method and apparatus for selecting a media processor to host a conference A system, method, apparatus, means, and computer program code for selecting a media processor to host a conference is provided. According to some embodiments, a... |
| US-7,702,937 |
Method and apparatus for operating a computer system by adjusting a
performance state of a processor resource A method, apparatus or stored program for adjusting the clock throttle rate of a central processing unit (CPU) included in a computer, in which the usage of the... |
| US-7,701,954 |
Gateway with voice In one aspect of the present invention, a network gateway is configured to facilitate on line and off line bi-directional communication between a number of near... |
| US-7,698,538 |
Method and apparatus for downloading program by using hand shaking in
digital signal processing A method and apparatus are provided for downloading a program by using hand-shaking in a digital signal processor (DSP), in which the program stored at an... |
| US-7,698,533 |
Configurable co-processor interface A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The coprocessor interface has an instruction transfer... |
| US-7,698,493 |
Methods and apparatus for translating write request messages in a
computing system Methods and apparatus are disclosed to translate memory write requests to be transmitted from a first processor to a second processor in a computing system, such... |
| US-7,694,174 |
Systems and methods for CPU repair Systems and methods for repairing a processor are provided. In one embodiment, a method for repairing a processor is provided that includes, for example, the... |
| US-7,694,158 |
Parallel processing method and system, for instance for supporting
embedded cluster platforms, computer program... A multi-processing system-on-chip including a cluster of processors having respective CPUs is operated by: defining a master CPU within the respective CPUs to... |
| US-7,694,111 |
Processor employing loadable configuration parameters to reduce or
eliminate setup and pipeline delays in a... A deep-pipeline system substantially reduces the overhead of setup delays and pipeline delays by dynamically controlling access of a plurality of configuration... |
| US-7,694,043 |
Method, system, for exchanging data via a buffer pool between a central
processing unit and input/output... A method is disclosed for exchanging data between a central processing unit (CPU) and an input/output processor (IOP). The CPU and IOP may both be senders or... |
| US-7,690,765 |
Central processor for a camera with printing capabilities A central processor for a camera having printing capabilities has a CPU core. A data cache is connected to the core. A vector processor is connected to the core... |
| US-7,685,331 |
Direct memory access controller A direct memory access controller (DMAC) is disclosed. In one case, the DMAC is configured to manage a DMA transmission of mass data with non-continuous... |
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