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United States Patent Application	20090273360
Kind Code	A1
Farnworth; Warren M. ;   et al.	November 5, 2009

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Claims

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1. An electronic circuit comprising:an external communications node;an internal circuit;control circuitry coupled to the external communications node and configured to sense one of a high current and a short circuit in the internal circuit, the control circuitry comprising:a PMOS transistor having a first doped region coupled to the external communications node, a gate, and a second doped region;a first resistance coupled between the external communications node and the gate of the transistor; anda second resistance coupled between the second doped region of the transistor and a reference voltage node; andswitching circuitry coupled to the second doped region and the internal circuit, the switching circuitry being configured to selectively isolate the internal circuit from the external communications node in response to receiving a signal from the second doped region.

2. The electronic circuit of claim 1, wherein the control circuitry further comprises:a second PMOS transistor having a first doped region coupled to the external communications node, a gate, and a second doped region coupled to the switching circuitry; andan inverter coupled between the switching circuitry and the gate of the second PMOS transistor.

3. The electronic circuit of claim 1, wherein the external communications node comprises a test node.

4. The electronic circuit of claim 3, wherein the test node comprises a probe pad.

5. The electronic circuit of claim 4, wherein the probe pad comprises a bond pad.

6. The electronic circuit of claim 1, wherein the first doped region comprise a source and the second doped region comprises a drain.

7. The electronic circuit of claim 1, wherein the first and second resistances comprise first and second resistive devices.

8. The electronic circuit of claim 1, wherein the reference voltage node is coupled to a supply voltage.

9. The electronic circuit of claim 8, wherein the supply voltage comprises a ground voltage.

10. The electronic circuit of claim 5, wherein the bond pad is configured to receive a supply voltage.

11. The electronic circuit of claim 5, wherein the bond pad is configured to receive a test voltage.

12. The electronic circuit of claim 1, wherein the internal circuit is coupled to the reference voltage node.

13. The electronic circuit of claim 1, wherein the control circuitry is coupled between the switching circuitry and the external communications node.

14. The electronic circuit of claim 1, wherein the first doped region of the transistor and the first resistance are directly connected to the external communications node.

15. A system comprising:control circuitry within an integrated circuit for sensing one of a high current and a short in an internal circuit of the integrated circuit; andcircuitry for isolating the internal circuit from circuitry external to the integrated circuit in response to the control circuitry sensing one of a high current and a short.

16. The system of claim 15, wherein the circuitry for isolation the internal circuit from circuitry external to the integrated circuit comprises one of a bipolar junction transistor and a micro-relay.

17. The system of claim 15, further comprising:isolating the internal circuit from another integrated circuit on a wafer.

18. The system of claim 15, further comprising:isolating the internal circuit from a pad.

19. The system of claim 18, wherein the pad comprises a bond pad.

20. The system of claim 18, wherein the pad comprises a probe pad.

21. The system of claim 15, further comprising:switching circuitry on the integrated circuit.

22. The system of claim 15, further comprising:switching circuitry located on a probe card.

23. The system of claim 15, wherein the circuitry for isolating the internal circuit from circuitry external to the integrated circuit automatically isolates the internal circuit.

24. A system comprising:control circuitry for sensing one of a high current and a short in an internal circuit of an integrated circuit; andswitching circuitry for automatically isolating the internal circuit from circuitry external to the integrated circuit in response to the control circuitry sensing one of a high current and a short.

25. The system of claim 24, wherein the control circuitry comprises control circuitry within the integrated circuit.

26. The system of claim 24, wherein the switching circuitry automatically isolates the internal circuit when sensing a short to ground.

27. The system of claim 24, wherein the switching circuitry automatically isolates the internal circuit when sensing excessive current.

28. The system of claim 24, wherein the switching circuitry automatically isolates the internal circuit when sensing high voltage.

29. The system of claim 24, wherein the switching circuitry automatically isolates the internal circuit when sensing low voltage.

30. The system of claim 24, wherein the switching circuitry automatically isolates the internal circuit when the applied voltage is no longer applied.

31. A system comprising:control circuitry for sensing a short in an internal circuit of the integrated circuit;a bipolar junction transistor for isolating the internal circuit from circuitry external to the integrated circuit in response to the control circuitry sensing one of a high current and a short.

32. A system comprising:control circuitry for sensing a short in an internal circuit of the integrated circuit; anda micro-relay for isolating the internal circuit from circuitry external to the integrated circuit in response to the control circuitry sensing one of a high current and a short.

33. The system of claim 32, wherein the control circuitry comprises circuitry for sensing current drawn by the internal circuit that exceeds a predetermined threshold and for outputting the control signal in response thereto.

34. The electronic system of claim 33, wherein the control circuitry comprises circuitry for sensing a voltage applied to the internal circuit that is below a predetermined threshold and for outputting the control signal in response thereto.

35. A method for testing a plurality of integrated circuits of a semiconductor die of a plurality of semiconductor die of a wafer comprising:sensing one of a high current level and a short in a first internal circuit of the plurality of integrated circuits of a first semiconductor die of the plurality of semiconductor die using control circuitry; andautomatically isolating the first internal circuit of the first semiconductor die from circuitry external to the integrated circuit in response to the control circuitry sensing a one of a high current level and a short in the first internal circuit of the plurality of integrated circuits using circuitry for automatically isolating the first internal circuit of the first semiconductor die from circuitry external to the integrated circuit.

36. The method of claim 35, further comprising:sensing another internal circuit of the plurality of integrated circuits of a first semiconductor die of the plurality of circuits of the first semiconductor die of the plurality of semiconductor dice using control circuitry within an integrated circuit for sensing one of a high current level and a short; andautomatically isolating the another internal circuit of the first semiconductor die from circuitry external to the another integrated circuit in response to the control circuitry sensing one of a high current level and a short in the another internal circuit of the plurality of integrated circuits using circuitry for automatically isolating the another internal circuit of the first semiconductor die from circuitry external to the integrated circuit.

37. The method of claim 35, further comprising:disconnecting the first internal circuit of the first semiconductor die upon detecting one of one of a high current level and a short in the first internal circuit of the first semiconductor die.

38. The method of claim 35, further comprising:sensing one of a high current level and a short for each internal circuit of the plurality of integrated circuits of the first semiconductor die of the plurality of semiconductor die; andautomatically isolating each internal circuit of the first semiconductor die from circuitry external to the integrated circuit in response to the control circuitry sensing one of a high current level and a short in an internal circuit of the plurality of integrated circuits using circuitry for automatically isolating the first internal circuit of the first semiconductor die from circuitry external to the integrated circuit.

39. The method of claim 35, further comprising:disconnecting the first semiconductor die from the plurality of semiconductor die having any internal circuit having one of a high current level and a short circuit.

40. The method of claim 39, further comprising:connecting the plurality of semiconductor die in parallel;sensing one of a high current level and a short in a first internal circuit of the plurality of integrated circuits of the plurality of semiconductor die connected in parallel using control circuitry; andautomatically isolating the first internal circuit of the plurality of semiconductor die connected in parallel from circuitry external to the integrated circuit in response to the control circuitry sensing a one of a high current level and a short in the first internal circuit of the plurality of integrated circuits using circuitry for automatically isolating the first internal circuit of the first semiconductor die from circuitry external to the integrated circuit.

41. The method of claim 40, further comprising:sensing another internal circuit of the plurality of integrated circuits of the plurality of semiconductor die connected in parallel of the plurality of circuits of the first semiconductor die of the plurality of semiconductor dice using control circuitry within an integrated circuit for sensing one of a high current level and a short; andautomatically isolating the another internal circuit of the plurality of semiconductor die connected in parallel from circuitry external to the another integrated circuit in response to the control circuitry sensing one of a high current level and a short in the another internal circuit of the plurality of integrated circuits using circuitry for automatically isolating the another internal circuit of the first semiconductor die from circuitry external to the integrated circuit.

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Description

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CROSS-REFERENCE TO RELATED APPLICATIONS

[0001]This application is a continuation of application Ser. No. 12/017,262 filed Jan. 21, 2008, pending, which is a divisional of application Ser. No. 11/607,162 filed Dec. 1, 2006, now U.S. Pat. No. 7,323,896 issued Jan. 29, 2008, which is a divisional of application Ser. No. 11/410,126, filed Apr. 24, 2006, now U.S. Pat. No. 7,212,020, issued May 1, 2007, which is a continuation of application Ser. No. 11/009,829, filed Dec. 10, 2004, now U.S. Pat. No. 7,034,561, issued Apr. 25, 2006, which is a continuation of application Ser. No. 10/690,496, filed Oct. 21, 2003, now U.S. Pat. No. 6,831,475, issued Dec. 14, 2004, which is a continuation of application Ser. No. 10/218,279, filed Aug. 13, 2002, now U.S. Pat. No. 6,636,068, issued Oct. 21, 2003, which is a continuation of application Ser. No. 09/944,509, filed Aug. 30, 2001, now U.S. Pat. No. 6,452,415, issued Sep. 17, 2002, which is a continuation of application Ser. No. 09/083,819, filed May 22, 1998, now U.S. Pat. No. 6,313,658, issued Nov. 6, 2001.

BACKGROUND OF THE INVENTION

[0002]1. Field of the Invention

[0003]This invention relates in general to integrated circuits (ICs) fabricated on semiconductor wafers and, more specifically, to devices and methods for isolating a short-circuited IC from other ICs on a semiconductor wafer so that, for example, probe testing may proceed on the other ICs on the wafer despite the presence of the short-circuited IC.

[0004]2. State of the Art

[0005]As shown in FIG. 1, integrated circuits (ICs) 10 are small electronic circuits formed on the surface of a wafer 12 of semiconductor material, such as silicon, in an IC manufacturing process referred to as "fabrication." Once fabricated, ICs 10 are electronically probed to evaluate a variety of their electronic characteristics. Probing typically involves positioning needle-like probes (not shown) onto bond pads 14 on the surfaces of ICs 10 to test the ICs 10 using various electronic signals supplied through the probes. As described in U.S. Pat. Nos. 5,059,899 and 5,214,657 to Farnworth et al., in some cases, ICs 10 are tested using test probes that contact probe pads 16 positioned on the surface of a semiconductor wafer 12 rather than, or in addition to, contacting bond pads 14 on the ICs 10.

[0006]Sometimes shorts develop in some of the ICs 10 on a semiconductor wafer 12 as a result of fabrication errors. These shorts can interfere with the probe testing described above in a variety of ways. For example, in some instances, a supply voltage V.sub.CC, provided to ICs 10 on a wafer 12 through probes contacting bond pads 14 on the ICs 10 or probe pads 16 on the wafer 12, may be shorted to ground through one of the ICs 10. As a result, over-current protection circuitry, such as a fuse, present in testing equipment that provides the supply voltage V.sub.CC to the probes, will likely "trip" the equipment off-line, causing a brief but significant delay in the manufacturing of ICs 10 while the equipment is reset. In addition, such a V.sub.CC-to-ground short in an IC 10 may make the entire wafer 12 untestable until the IC 10 with the short is identified and either repaired or disconnected, which involves a separate manual process that can cause additional delays in the manufacturing process.

[0007]In other instances, a test signal V.sub.TEST supplied to a group of ICs 10 on a semiconductor wafer 12 through a probe pad 16 on the wafer 12 may be distorted for all of the ICs 10 in the group by, for example, a V.sub.TEST-to-ground or a V.sub.TEST-to-V.sub.CC short in one of the ICs 10 in the group. This distortion may interfere with probe testing of all of the ICs 10 in the group, and may require that the IC 10 with the short be manually identified and repaired or disconnected before the ICs 10 in the group can be successfully probe tested.

[0008]Therefore, there is a need in the art for a device and method for isolating a short-circuited IC on a semiconductor wafer from other ICs on the wafer. Preferably, such a device and method should isolate a short-circuited IC before the IC interferes with probe testing of other ICs so the probe testing can continue uninterrupted.

BRIEF SUMMARY OF THE INVENTION

[0009]An inventive device for isolating a short-circuited integrated circuit (IC) from other ICs formed on the surface of a semiconductor wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.

[0010]Further embodiments of the present invention are directed to an IC including the control and switching circuitry described above, a semiconductor wafer including many of these ICs, and an electronic system, such as a computer system, including at least one of these ICs.

[0011]In an inventive method for testing ICs formed on the surface of a semiconductor wafer, control circuitry is provided in the ICs for sensing shorts in the ICs. The ICs are then tested, and if the control circuitry in one of the ICs senses a short, the short-circuiting IC is automatically switchably isolated from the other ICs.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0012]FIG. 1 is a prior art top view of a conventional semiconductor wafer showing interconnected integrated circuits (ICs) formed on the surface of the wafer;

[0013]FIG. 2 is a block diagram and a schematic of an IC including circuitry for isolating a short-circuiting circuit internal to the IC from a supply voltage V.sub.CC bond pad on the IC in accordance with the present invention;

[0014]FIG. 3 is a top view of a semiconductor wafer including interconnected ICs formed on its surface that are identical to the IC shown in FIG. 2;

[0015]FIG. 4 is a block diagram of an electronic system including the IC of FIG. 2;

[0016]FIG. 5 is a block diagram and a schematic of an IC including an alternative embodiment of circuitry for isolating a short-circuiting circuit internal to the IC from a supply voltage V.sub.CC bond pad on the IC in accordance with the present invention;

[0017]FIG. 6 is a block diagram and a schematic of another alternative embodiment of circuitry for isolating a short-circuiting circuit internal to an IC from a supply voltage V.sub.CC bond pad on the IC in accordance with the present invention; and

[0018]FIG. 7 is a block diagram and a schematic of still another alternative embodiment of circuitry for isolating a short-circuiting circuit internal to an IC from a supply voltage V.sub.CC bond pad on the IC in accordance with the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0019]As shown in FIG. 2, an integrated circuit (IC) 20 in accordance with the present invention includes control circuitry 22 for sensing a short in a circuit 24 internal to the IC 20 and switching circuitry 26 for isolating the internal circuit 24 from a supply voltage V.sub.CC bond pad 28 on the IC 20 in response to the control circuitry 22 sensing the short. By isolating the short-circuited internal circuit 24 from the supply voltage V.sub.CC bond pad 28, the present invention can prevent the short from "tripping" probe test equipment (not shown) supplying the supply voltage V.sub.CC to a semiconductor wafer (not shown) during probe testing of the wafer.

[0020]It should be understood that the IC may comprise any IC, including, for example, a Dynamic Random Access Memory (DRAM) IC and a Static RAM (SRAM) IC. It should also be understood that although the control circuitry and switching circuitry will be described with respect to specific circuitry, the present invention includes within its scope any control circuitry and any switching circuitry capable of performing the functions as described. Also, although the control circuitry will be described as sensing the short in the internal circuit by sensing excess current drawn by the internal circuit, the control circuitry may instead be constructed to sense abnormally high or low voltages within the internal circuit indicative of a short circuit. Further, it should be understood that while the present invention is considered most applicable to probe testing, its applicability is not limited to probe testing. In addition, it should be understood that the present invention can be used to isolate short-circuiting internal circuitry of an IC from a wide variety of circuitry external to the IC, and thus is not limited to isolating internal circuitry from a supply voltage V.sub.CC bond pad.

[0021]Under normal probe testing conditions of the IC 20, when a short circuit does not exist in the internal circuit 24, a ground voltage V.sub.SS applied at the gate of a switching PMOS transistor 32 through a large resistance device 34 (e.g., more than 1 M.OMEGA.) turns the switching PMOS transistor 32 on. The ground voltage V.sub.SS is also applied at the input of an inverter 36, which then outputs a high voltage at the gate of a hysteresis PMOS transistor 38, causing the hysteresis PMOS transistor 38 to be off. Because the switching PMOS transistor 32 is on, the supply voltage V.sub.CC applied at the bond pad 28 causes a current I to flow through a sensing resistance device 40 and the switching PMOS transistor 32 to the internal circuit 24.

[0022]The amount of resistance R of the sensing resistance device 40 is selected so that, under normal probe testing conditions, the current I drawn by the internal circuit 24 causes a voltage drop V (equal to IHR) across the sensing resistance device 40 that is less than the threshold voltage *V.sub.T* of a sensing PMOS transistor 42. As a result, the sensing PMOS transistor 42 is off.

[0023]When a short circuit (e.g., a short circuit to ground) does exist in the internal circuit 24, the internal circuit 24 rapidly draws excessive current I through the sensing resistance device 40, causing the voltage drop V across the sensing resistance device 40 to exceed the threshold voltage *V.sub.T* of the sensing PMOS transistor 42. As a result, the sensing PMOS transistor 42 turns on, thereby applying the supply voltage V.sub.CC at the gate of the switching PMOS transistor 32 and at the input of the inverter 36. Application of the supply voltage V.sub.CC at the input of the inverter 36 causes the inverter 36 to output a low voltage at the gate of the hysteresis PMOS transistor 38, thereby turning the hysteresis PMOS transistor 38 on and reinforcing application of the supply voltage V.sub.CC at the gate of the switching PMOS transistor 32. This causes the switching PMOS transistor 32 to turn off, thereby interrupting the excessive current I and isolating the short-circuited internal circuit 24 from the bond pad 28.

[0024]Because the current I is interrupted, the voltage drop V across the sensing resistance device 40 drops to zero, causing the sensing PMOS transistor 42 to turn off. Despite this, the switching PMOS transistor 32 remains off, because feedback of the supply voltage V.sub.CC from the drain of the hysteresis PMOS transistor 38 to the input of the inverter 36 causes the inverter 36 to continue to output a low voltage at the gate of the hysteresis PMOS transistor 38, thereby causing the hysteresis PMOS transistor 38 to remain on and to continue to apply the supply voltage V.sub.CC to the gate of the switching PMOS transistor 32. The IC 20 remains in this state, with the short-circuited internal circuit 24 isolated from the bond pad 28, and hence from other ICs under test, by the switching PMOS transistor 32 until the supply voltage V.sub.CC is no longer applied to the bond pad 28, at which point the control circuitry 22 is reset.

[0025]As shown in FIG. 3, multiple ICs 20 are formed and interconnected on the surface of a semiconductor wafer 50 in accordance with the present invention. As shown in FIG. 4, an electronic system 52, such as a computer system, includes an input device 54, an output device 56, a processor 58, and a memory device 60 incorporating the IC 20 of FIGS. 2 and 3.

[0026]As shown in FIG. 5, an IC 70 in accordance with an alternative embodiment of the present invention includes a fuse 72 for sensing a short in a circuit 74 internal to the IC 70 and for isolating the internal circuit 74 from a supply voltage V.sub.CC bond pad 78 on the IC 70 when excessive current is drawn by the short.

[0027]As shown in FIG. 6 in another alternative embodiment of the present invention, an IC 80 includes control circuitry 82 for sensing a short in a circuit 84 internal to the IC 80 and switching circuitry 86 for isolating the internal circuit 84 from a supply voltage V.sub.CC bond pad 88 on the IC 80 in response to the control circuitry 82 sensing the short. By isolating the short-circuited internal circuit 84 from the supply voltage V.sub.CC bond pad 88, the present invention can prevent the short from "tripping" probe test equipment (not shown) supplying the supply voltage V.sub.CC to a semiconductor wafer (not shown) during probe testing of the wafer.

[0028]Under normal probe testing conditions of the IC 80, when a short circuit does not exist in the internal circuit 84, a series of biasing resistors 90, 92, and 94 biases the base 96 of a switching bipolar junction transistor (BJT) 98 at a voltage intermediate the supply voltage V.sub.CC and a ground voltage V.sub.SS so that the BJT 98 is on. A voltage taken from between the biasing resistors 92 and 94 and applied at the input of an inverter 100 causes the inverter 100 to output a high voltage to the gate of a hysteresis PMOS transistor 102, causing the hysteresis PMOS transistor 102 to be off. Because the switching BJT 98 is on, the supply voltage V.sub.CC applied at the bond pad 88 causes a current I to flow through a resistor 104 and the BJT 98 to the internal circuit 84.

[0029]The amount of resistance R of the resistor 104 is selected so that, under normal probe testing conditions, the current I drawn by the internal circuit 84 causes a voltage drop V (equal to IHR) across the resistor 104 that is less than the threshold voltage *V.sub.T* of a sensing PMOS transistor 106. As a result, the sensing PMOS transistor 106 is off.

[0030]When a short circuit (e.g., a short circuit to ground) does exist in the internal circuit 84, the internal circuit 84 rapidly draws excessive current I through the resistor 104, causing the voltage drop V across the resistor 104 to exceed the threshold voltage *V.sub.T* of the sensing PMOS transistor 106. As a result, the sensing PMOS transistor 106 turns on, thereby applying the supply voltage V.sub.CC at the base 96 of the switching BJT 98 and raising the voltage applied at the input to the inverter 100. The rising voltage at the input of the inverter 100 causes the inverter 100 to output a low voltage at the gate of the hysteresis PMOS transistor 102, thereby turning the hysteresis PMOS transistor 102 on and reinforcing application of the supply voltage V.sub.CC at the base 96 of the switching BJT 98. This causes the switching BJT 98 to turn off, thereby interrupting the excessive current I and isolating the short-circuited internal circuit 84 from the bond pad 88.

[0031]Because the current I is interrupted, the voltage drop V across the resistor 104 drops to zero, causing the sensing PMOS transistor 106 to turn off. Despite this, the switching BJT 98 remains off, because the raised voltage at the input of the inverter 100 causes the inverter 100 to keep the hysteresis PMOS transistor 102 on, allowing the hysteresis PMOS transistor 102 to continue to apply the supply voltage V.sub.CC to the base 96 of the BJT 98. The IC 80 remains in this state, with the short-circuited internal circuit 84 isolated from the bond pad 88, and hence from other ICs under test, by the switching BJT 98 until the supply voltage V.sub.CC is no longer applied to the bond pad 88, at which point the control circuitry 82 is reset.

[0032]It should be understood that the switching BJT 98 may be implemented on the IC 80, as is shown in FIG. 6, in a BiCMOS configuration or, alternatively, may be implemented on a probe card contacting the bond pad 88 or between ICs on a semiconductor wafer.

[0033]As shown in FIG. 7 in still another alternative embodiment of the present invention, an IC 110 includes control circuitry 112 for sensing a short in a circuit 114 internal to the IC 110 and a micro-relay 116 for isolating the internal circuit 114 from a supply voltage V.sub.CC bond pad 118 on the IC 110 in response to the control circuitry 112 sensing the short. By isolating the short-circuited internal circuit 114 from the supply voltage V.sub.CC bond pad 118, the present invention can prevent the short from "tripping" probe test equipment (not shown) supplying the supply voltage V.sub.CC to a semiconductor wafer (not shown) during probe testing of the wafer.

[0034]Under normal probe testing conditions of the IC 110, when a short circuit does not exist in the internal circuit 114, the control circuitry 112 senses no short in the internal circuit 114, so it causes the micro-relay 116 to close and allow a current I to flow to the internal circuit 114.

[0035]When a short circuit (e.g., a short circuit to ground) does exist in the internal circuit 114, the internal circuit 114 rapidly draws excessive current I. The control circuitry 112 detects this excessive current I and, as a result, causes the micro-relay 116 to open, thereby isolating the internal circuit 114 from the bond pad 118. The control circuitry 112 remains in this state until reset by the voltage at the bond pad 118 dropping to zero and then rising again to the supply voltage V.sub.CC.

[0036]It should be understood that the micro-relay may be created using silicon micro-machining techniques, and may comprise a capacitively or inductively controlled relay.

[0037]Although the present invention has been described with reference to particular embodiments, the invention is not limited to these described embodiments. For example, while the various steps of operating the inventive device, and hence the various steps of the inventive method, have been described as occurring in a particular order, it will be understood that these steps need not necessarily occur in the described order to fall within the scope of the present invention. Thus, the invention is limited only by the appended claims, which include within their scope all equivalent devices and methods that operate according to the principles of the invention as described.

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