At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.
Apparatus for strictly ordered input/output operations for interrupt
A method and apparatus which maintains strict ordering of processor cycles to guarantee that a processor write, such as an EOI instruction, is not executed to...
Distributed machine state controlled processor system with a CPU clocked
with a reference signal delayed from a...
A controller (MSC) for generating a basic control signal to permit a CPU to access to a resource in a processor system is arranged in each of local control...
Potty trainer timepiece
A device for time conditioning children. The device comprises an alarm circuit for producing an alarm signal, an alarm timer for timing an alarm interval and...
Input/output command issuing control system in data processing system
An I/O command issuing control system is applied to a data processing system including a processor module provided with a CPU and an adaptor module which is...
Apparatus for queing and storing data writes into valid word patterns
A digital computer system has a central processor unit (CPU) and a store queue facility. The store queue facility receives full digital words or segments thereof...
Multiprocessor cache coherency tester that exercises the coherency logic
exhaustively and also detects errors...
A cache coherency test exercises cache coherency logic exhaustively such that any cache coherency failures liable to occur will occur. The CPU(s) which caused...
Second level cache controller unit and system
A second level cache memory controller, implemented as an integrated circuit unit, operates in conjunction with a secondary random access cache memory and a main...
CPU lock logic for corrected operation with a posted write array
A shared bus arbitration system is disclosed which provides logic allowing multiple processors to co-exist on a common bus. In the present invention, the host...
Method and apparatus for concurrency of bus operations
A method and apparatus for performing concurrent operations on the host bus, expansion bus, and local I/O bus as well as the processor bus connecting the...
Method and apparatus for detecting epileptic seizures
A method and apparatus for accurately determining the onset or occurrence of an epileptic seizure is disclosed. The system includes an electroencephalograph...
Telecommunication switch with programmable communications services
A telecommunications switch which may be configured to provide a variety of user-programmable communications or call processing services. Such services may be...
Serial communication peripheral integrated electronic circuit that
recognizes its unique address before the...
A peripheral integrated electronic circuit of the type having an interface for serially transferring data between it and a central processing unit ("CPU") in a...
Recovery of cached data from a malfunctioning CPU
Recovery of data from a store-to cache in a malfunctioning CPU, is accomplished without exercising the hardware of the malfunctioning CPU. A data path which is...
Apparatus for managing page zero accesses in a multi-processor data
Apparatus for use in a multi-CPU data processing system (10) wherein each CPU (12-18) is coupled to a common bus (20) and through the common bus to a main memory...
Error correction code pipeline for interleaved memory system
A data stream process pipeline and method of transferring data from a storage device to a central processor unit (CPU) or cache memory includes an input latch...
Virtual storage data processor with enhanced dispatching priority
allocation of CPU resources
Dispatching improvements in operating systems are described for multiprogrammed data processing systems. A common priority dispatching mechanism for applications...
System crash detect and automatic reset mechanism for processor cards
A hardware and software mechanism is provided for ensuring that a feature processor card, included with other feature cards in a host system, can be reset...
Multiprocessor system with program change function controlled by one
In a multiprocessor system with program change function according to the present invention, a special CPU among a plurality of CPU's inputs program data from...
Graphic information processing system having a RISC CPU for displaying
information in a window
A computer related system including a reduced instruction set computer (RISC) central processing unit for effectively processing a data bottleneck phenomenon due...
Stage saving and restoring hardware mechanism
A hardware mechanism capable of performing state saving and restoring operations, for use in a computer environment having a computer system having a central...
Processor system with dual clock
The present invention provides a means for operating the CPU in a single chip microprocessor at a multipe of the cycle speed of the memory bus. With the present...
Digital processor with bit mask for counting registers for fast register
A high-performance, pipelined CPU in which an improved method is used for saving registers in memory upon the occurrence of a procedure CALL or RETURN. The...
Method and apparatus for transmitting graphics command in a computer
A residue buffer, for temporary storage of portions of transmissions from a CPU to a graphics processor. Graphics commands are transmitted, in transmission units...
Computer scalable visualization system
A scalable visualization system includes a plurality of scalable tiles (10) that each comprise a display portion (18) and a processing portion (20). Each of the...
Fault-tolerant computer system with auto-restart after power-fall
A fault-tolerant computer system employs a power supply system including a battery backup so that upon AC power failure the system can execute an orderly...
Multiple-processor computer system with asynchronous execution of
identical code streams
A fault-tolerant computer system employs multiple identical CPUs executing the same instruction stream, each with their own independent memory. The multiple CPUs...
Processor system with writeback cache using writeback and non writeback
transactions stored in separate queues
A pipelined CPU executing instructions of variable length, and referencing memory using various data widths. A writeback cache is used (instead of writethrough)...
Reduced instruction set computer system including apparatus and method
for coupling a high performance RISC...
Methods and apparatus are disclosed for transferring data to and from the Local Bus of a reduced instruction set computer (RISC) system, to which a first set of...
High-speed color saturation converter for digital color data
A high-speed saturation converter for a color image, comprising first R, G, and B image memories for storing digital color image data separated into R, G, and B,...
CPU with integrated multiply/accumulate unit
An integrated circuit (IC) processor architecture is disclosed that implements hardware, signal processing (DSP) functions with less digital improved speed and a...
Microprocessor and method for setting up its peripheral functions
A single chip microprocessor 1 includes a CPU 2 and a sub-processor 5 for software implementation of peripheral functions of the microprocessor 1. Sub-processor...
In a microcomputer having two program execution states including a supervisor state and a user state, there is disposed a flag or a register having such a flag...
Method and apparatus for assembling a composite image from a plurality
of data types
A method and apparatus for combining multiple image data files of differing sizes, resolutions, and formats in real time into a single data stream for conversion...
Memory mapping and special write detection in a system and method for
simulating a CPU processor
The system and method of this invention simulates the flow of control of an application program targeted for a specific instruction set of a specific processor...
Method and apparatus for address space aliasing to identify pixel types
A CPU or other graphics processor provides a pixel data stream to a graphics controller over a system bus. The pixel data stream includes a graphics controller...
Processor with a plurality of microprogrammed units, with anticipated
execution indicators and means for...
A data processing system having processors with large instruction sets optimized for the execution of brief instructions. The processor (CPU) comprises a...
Processor having a plurality of CPUS with one CPU being normally
connected to common bus
A processor for constructing a single processor system or multiprocessor system comprises, within a base processor element constituting the processor, two CPU...
Fault-tolerant computer system with online recovery and reintegration of
A computer system in a fault-tolerant configuration employs multiple identical CPUs executing the same instruction stream, with multiple, identical memory...
Cache subsystem for microprocessor based computer system with
synchronous and asynchronous data path
An integrated circuit, for use as a cache subsystem, implements a cache static random access memory (SRAM) storage array, a central processor unit (CPU) bus...
Preemption control for central processor with cache
A logic controlled gate is inserted in the arbitration logic of a computer system that supports multiple masters on a data bus. In such a system with arbitration...
Transparent system interrupts with automated halt state restart
A dedicated memory area is provided on a microprocessor system for storing a customizable system interrupt service routine, processor state data at the time of...
Modular user programmable telecommunications system with distributed
A telecommunications system is provided to connect a plurality of dissimilar types of subscriber telecommunications devices and to provide integrated...
Remote management system for photographic equipment
A printer processor, a film processor, and a densitometer are connected to a personal computer via a port controller. To diagnose the operational condition of...
Compact data processor having a tilting and sliding display
A data processor composed of: a main body including a CPU, a keyboard provided at the top of the main body, a pair of sliding rails provided at both sides of the...
One-chip data processor with built-in A/D converter for automatically
repeating A/D conversions without...
A data processing unit according to the present invention has a central processing unit, and an analog-to-digital converter circuit associated with a plurality...
Direct memory access apparatus in image processing system and external
storage device used therein
A direct memory access apparatus includes a CPU, and data of one byte or more to be transferred is stored in a working RAM of the CPU or an external storage...
System and method for drawing antialiased polygons
A system (30) draws antialiased polygons. A CPU (32) is connected to a floating point processor (FPU) (34) by bus (36). The CPU (32) is connected by a 32-bit...
Hardware based interface for mode switching to access memory above one
A relatively fast system control processor, such as an Intel 8051, is substituted for an Intel 8042 microprocessor in a PC/AT type compatible personal computer....
Power up/power down controller and power fail detector for processor
A power fail control system for a CPU (10) and external memory (16) utilizes a controller (18). The controller (18) is operable to detect an early power fail...
Personal computer having dedicated processors for peripheral devices
interconnected to the CPU by way of a...
A plurality of processors form a network used to communicate with one or more peripheral devices and the system control processor. One processor is dedicated to...