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Decoupling apparatus for verification of a processor independent from an
associated data processing system
In a data processing system having a plurality of CPUs, each CPU is operatively connected to other portions of the data processing system through a system...
Apparatus for displaying musical notes indicative of pitch and time value
An input audio signal is analog-to-digital (AD) converted into digital data which is processed by a central processing unit (CPU) for determining pitch of each...
Image processing system
An image processing system is disclosed which includes: a control computer which has a CPU and a main memory therein; and an image memory section which is...
Data logging device
To allow a salesman to record data relating to merchandise items which are to be ordered, a logging device comprises a casing in which are housed a keyboard, a...
Voice/text storage and retrieval system
The Voice/Text Storage System provides for the storage of digital data and digitized voice signals and is particularly suited for applications such as voice mail...
CPU with multi-stage mode register for defining CPU operating
environment including charging its communications...
A central processor unit (CPU) is capable of being connected in data processing systems having diverse logical operating characteristics. The CPU contains an...
Programmable game with virtual CPU's sharing ALU and memory for
simultaneous execution of independent game inputs
A two player game apparatus includes the inputs for the first and second player, together with display for each player with a common display for providing the...
Musical note display device
An input audio signal is AD converted into digital data which is processed by a central processing unit (CPU) in which Fast Fourier Transform (FFT) operation and...
Computing system with multifunctional arithmetic logic unit in single
A computing system includes a central processor unit (CPU) in combination with external memory units. The CPU includes an arithmetic logic (ALU), an instruction...
System for independent cache-to-cache transfer
The disclosure provides a plurality of embodiments for controlling the bus paths for a line of data from any cache in a multiprocessing system (MP) to any...
Write protected memory
An interactive terminal includes a central processor unit (CPU) having a microprocessor and a random access memory (RAM). Signals from the microprocessor place...
Central processor utilization monitor
Data relative to code instruction use of a central processor unit (CPU) is collected by accumulating counts of code instructions to be executed upon termination...
An intelligent asynchronous controller (IAC) for use in operably coupling a plurality of asynchronous input/output (I/O) devices to a host central processing...
Data transfer system for data entry system
A data transfer system in which a data entry system is converted from manual operation to automatic reading in a computer system, thereby to save time in the...
Page storage control methods and means
The embodiment provides an independent data bus path between a random access page storage (PS), and a main storage (MS), wherein this independent data bus does...
Apparatus for microprocessor address bus testing
An address bus of a central processor unit (CPU) is tested by generating repetitive "no operation" (NO OP) instructions. A microprocessor in the CPU receives the...
Audio/visual home computer and game apparatus
A home computer system provides a video processor for use with a television receiver. The video processor can selectively perform a variety of modifications to...
Method and apparatus for initiating the execution of instructions using
a central pipeline execution unit
A method and a central execution pipeline unit for initiating the execution of instructions of a synchronous central processor unit (CPU) of a general-purpose...
Method and apparatus for simultaneously displaying data indicative of
activity levels at multiple digital test...
A digital test point monitoring system for continuously monitoring n digital test points (where "n" is any desired whole integer)--test points which may, for...
Device for controlling the fuel-feed to an internal combustion engine
A control device for the fuel feed actuators of an internal combustion engine comprises a detector for detecting a first engine parameter (e.g. engine RPM),...
Keyboard identification sequence
In combination with a host processor CPU, means are provided to a standard computer terminal keyboard to reconfigure an identity change of the keyboard for...
Data processing system having redundant control processors for fault
A data processing system including a control store for storing a microprogram constituted by a number of microinstructions, first and second control processors...
Repeatered, multi-channel fiber optic communication network having fault
A repeatered, multichannel fiber optic communication network includes a plurality of full duplex fiber optic channels and one or more auxiliary channels. In...
Single chip microcomputer with external decoder and memory and internal
logic for disabling the ROM and...
A data processor system having a total memory capacity, an integrated circuit chip having thereon a central processing unit (CPU), a ROM, a RAM, a first decoder...
Digital fluorographic processor control
A method of controlling a digital video processor in a digital fluorography system wherein the electronic components of the processor are variously configured to...
Block transfers of information in data processing networks
Secondary storage subsystems exchange messages and data with host data processing systems and also forward messages between host systems. Host systems thereby...
Data processor including a multiple word processing method and device
An initialization routine provides to a CPU an instruction to be executed and multiple words of input data to be processed by the instruction. The CPU stores the...
Data processing system using a high speed data channel for providing
direct memory access for block data transfers
A data processing system having a central processor unit (CPU) and a memory and further including a high speed, or "burst multiplexer", channel for permitting...
Method and apparatus for direct memory access in a data processing system
The method and apparatus in a microprocessor-based data processing system which allows direct access to main memory associated with a central processing unit...
Store-in-cache processor means for clearing main storage
Inhibit means prevents a store-in-cache (SIC) from requesting or receiving any line fetch from MS when a clear line (CL) command is issued by a CPU to main...
Cache storage line shareability control for a multiprocessor system
A multiprocessor (MP) system is described having central processors (CPs) in which each CP has a store-in-cache (SIC) with an associated processor directory...
Interface apparatus for data transfer through an input/output
multiplexer from plural CPU subsystems to...
In a data processing unit, apparatus permits more than one central processing unit and associated control interface unit to transfer data to an input/output...
Multiprocessor system with apparatus for propagating cache buffer
invalidation signals around a circular loop
This data processing system includes a main memory which is shared by a plurality of central processor units (CPUs) which are also coupled in cascade in a closed...
Data processing system including internal register addressing
In a multi-processor system of the type in which each processor is provided with its own unique bus which has an addressing system organized in such a manner...
Data processing system having data entry backspace character apparatus
In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of data,...
Distributed control memory network
A computer-controlled distributed communication system in which there is a system controller and a plurality of group controllers all interchanging information...
Dot matrix type running display panel for use in electronic calculators
or the like
An electronic calculator with a dot matrix display panel capable of displaying characters, symbols or other patterns is implemented with a central processor unit...
Modular terminal system using a common bus
A modular terminal system (10) employs a CPU module (22) connected via a bus (20) to at least one slave module (24, 26, 28, 32, 36). An error condition is...
Programmable I/O device identification
A computer system having a CPU connected to I/O devices via a channel sets addresses into the I/O devices by the CPU. The I/O devices, for purposes of control,...
Data processor apparatus for multitariff meter
The meter includes a kilowatthour register which is continuously engaged as well as at least one special register (kilowatthour or demand) which is selectively...
Cache memory command buffer circuit
In a computer system, with a system interface unit (SIU) for controlling data transfers between a lower speed main memory and either a central processor unit...
Data-processing apparatus having improved interrupt handling processor
The data-processing apparatus of this invention comprises a central processing unit (hereinafter referred to as the "CPU"), and a plurality of a groups of memory...
Digital multifrequency signal generator
Multifrequency (FIGS. 2 and 4) signals are generated by employing a microcomputer system (500) in conjunction with a digital-to-analog converter (506) and filter...
A computer terminal is disclosed which may advantageously be employed as a video display terminal having editing capabilities. The terminal is a processor driven...
Method and system for controlling input/output in process control
Novel method and system for controlling input/output in a process control wherein state signals of object processes to be controlled are applied to a CPU via a...
Controller device with diagnostic capability for use in interfacing a
central processing unit with a peripheral...
A controller for interfacing a central processor unit (CPU) to a peripheral storage device which can be tested for proper operation independent of the peripheral...
CPU Employing micro programmable control for use in a data processing
A microprogrammed processor having a versatile hardware and data path configuration in which control signals for data paths, the ALU function, the shifter and...
Cache memory utilizing selective clearing and least recently used
An apparatus is disclosed herein for providing faster memory access for a CPU by utilizing a least recently used scheme for selecting a storage location in which...
Protection apparatus for multiple processor systems
In a data protection apparatus for a multiple CPU system having a common or multiported bulk memory, an interface structure is associated with each of the CPU's....
Multi-processor system employing job-swapping between different priority
A multi-processor system wherein a plurality of priority-designated central processor units (CPUs) are interconnected by a program control memory which operates...